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/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dmep-rhcop.cpu22 ;; This coprocessor definition is being used to verify vliw mode behaviour.
24 ;; a real coprocessor. The hardware is defined in mep-core.cpu.
31 (comment "64-bit coprocessor registers for rh coprocessor for core 1")
41 (comment "32-bit coprocessor registers for rh coprocessor for core 1")
51 (comment "Coprocessor control registers for rh coprocessor for core 1")
140 ; new nops are defined in new coprocessor insn sets.
177 (dncp116i movcp16 "16-bit coprocessor move insn"
185 (dncp116i movcp16a "16-bit coprocessor move insn"
193 (dncp116i movcp16b "16-bit coprocessor move insn"
201 (dncp116i cp16nop "16-bit coprocessor nop"
[all …]
H A Diq2000m.cpu121 ; Architectural and coprocessor instructions.
182 (dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
188 (dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
194 (dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
200 (dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
216 (dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
222 (dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
228 (dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
234 (dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
324 (dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
[all …]
H A Dmep-c5.cpu106 (dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
116 (dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
125 (dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
135 (dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
145 (dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
154 (dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
164 (dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
174 (dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
H A Dmep-fmax.cpu25 ; specified below for each ME_MODULE using this coprocessor.
26 ; This coprocessor requires only the 32 bit insns in the core.
104 ; Given a coprocessor register number N, expand to a
109 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
112 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
129 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
132 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
H A Dmep.opc84 /* A mask for all ISAs executed by a VLIW coprocessor. */
967 /* Now all that is left to be processed is the coprocessor insns
1078 16 bit core insn (core) and 16 bit coprocessor insn (cop1)
1080 32 bit coprocessor insn (cop1)
1083 no 16 bit coprocessor insns have been specified.
1086 16 bit core insn (core) and 48 bit coprocessor insn (cop1)
1087 32 bit core insn (core) and 32 bit coprocessor insn (cop1)
1088 64 bit coprocessor insn (cop1)
1090 The framework for an internally parallel coprocessor is also
1091 present (2nd coprocessor insn is cop2), but at this time it
[all …]
H A Dmep-core.cpu60 (comment "MeP coprocessor instruction set")
68 (comment "MeP coprocessor instruction set")
76 (comment "MeP coprocessor instruction set")
84 (comment "MeP coprocessor instruction set")
273 (comment "64-bit coprocessor registers")
282 (comment "64-bit coprocessor registers, pending writes")
290 (comment "32-bit coprocessor registers")
298 ;; Given a coprocessor control register number N, expand to a
509 ; These are all for the coprocessor opcodes
573 (comment "coprocessor code")
[all …]
/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dmep-rhcop.cpu22 ;; This coprocessor definition is being used to verify vliw mode behaviour.
24 ;; a real coprocessor. The hardware is defined in mep-core.cpu.
31 (comment "64-bit coprocessor registers for rh coprocessor for core 1")
41 (comment "32-bit coprocessor registers for rh coprocessor for core 1")
51 (comment "Coprocessor control registers for rh coprocessor for core 1")
140 ; new nops are defined in new coprocessor insn sets.
177 (dncp116i movcp16 "16-bit coprocessor move insn"
185 (dncp116i movcp16a "16-bit coprocessor move insn"
193 (dncp116i movcp16b "16-bit coprocessor move insn"
201 (dncp116i cp16nop "16-bit coprocessor nop"
[all …]
H A Diq2000m.cpu121 ; Architectural and coprocessor instructions.
182 (dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
188 (dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
194 (dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
200 (dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
216 (dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
222 (dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
228 (dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
234 (dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
324 (dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
[all …]
H A Dmep-c5.cpu106 (dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
116 (dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
125 (dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
135 (dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
145 (dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
154 (dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
164 (dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
174 (dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
H A Dmep-fmax.cpu25 ; specified below for each ME_MODULE using this coprocessor.
26 ; This coprocessor requires only the 32 bit insns in the core.
104 ; Given a coprocessor register number N, expand to a
109 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
112 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
129 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
132 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
H A Dmep-core.cpu60 (comment "MeP coprocessor instruction set")
68 (comment "MeP coprocessor instruction set")
76 (comment "MeP coprocessor instruction set")
84 (comment "MeP coprocessor instruction set")
273 (comment "64-bit coprocessor registers")
282 (comment "64-bit coprocessor registers, pending writes")
290 (comment "32-bit coprocessor registers")
298 ;; Given a coprocessor control register number N, expand to a
509 ; These are all for the coprocessor opcodes
573 (comment "coprocessor code")
[all …]
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dmep-rhcop.cpu22 ;; This coprocessor definition is being used to verify vliw mode behaviour.
24 ;; a real coprocessor. The hardware is defined in mep-core.cpu.
31 (comment "64-bit coprocessor registers for rh coprocessor for core 1")
41 (comment "32-bit coprocessor registers for rh coprocessor for core 1")
51 (comment "Coprocessor control registers for rh coprocessor for core 1")
140 ; new nops are defined in new coprocessor insn sets.
177 (dncp116i movcp16 "16-bit coprocessor move insn"
185 (dncp116i movcp16a "16-bit coprocessor move insn"
193 (dncp116i movcp16b "16-bit coprocessor move insn"
201 (dncp116i cp16nop "16-bit coprocessor nop"
[all …]
H A Diq2000m.cpu121 ; Architectural and coprocessor instructions.
182 (dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
188 (dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
194 (dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
200 (dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
216 (dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
222 (dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
228 (dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
234 (dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
324 (dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
[all …]
H A Dmep-c5.cpu106 (dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
116 (dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
125 (dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
135 (dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
145 (dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
154 (dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
164 (dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
174 (dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
H A Dmep-fmax.cpu25 ; specified below for each ME_MODULE using this coprocessor.
26 ; This coprocessor requires only the 32 bit insns in the core.
104 ; Given a coprocessor register number N, expand to a
109 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
112 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
129 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
132 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
H A Dmep.opc84 /* A mask for all ISAs executed by a VLIW coprocessor. */
966 /* Now all that is left to be processed is the coprocessor insns
1077 16 bit core insn (core) and 16 bit coprocessor insn (cop1)
1079 32 bit coprocessor insn (cop1)
1082 no 16 bit coprocessor insns have been specified.
1085 16 bit core insn (core) and 48 bit coprocessor insn (cop1)
1086 32 bit core insn (core) and 32 bit coprocessor insn (cop1)
1087 64 bit coprocessor insn (cop1)
1089 The framework for an internally parallel coprocessor is also
1090 present (2nd coprocessor insn is cop2), but at this time it
[all …]
H A Dmep-core.cpu60 (comment "MeP coprocessor instruction set")
68 (comment "MeP coprocessor instruction set")
76 (comment "MeP coprocessor instruction set")
84 (comment "MeP coprocessor instruction set")
273 (comment "64-bit coprocessor registers")
282 (comment "64-bit coprocessor registers, pending writes")
290 (comment "32-bit coprocessor registers")
298 ;; Given a coprocessor control register number N, expand to a
509 ; These are all for the coprocessor opcodes
573 (comment "coprocessor code")
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dmep-rhcop.cpu22 ;; This coprocessor definition is being used to verify vliw mode behaviour.
24 ;; a real coprocessor. The hardware is defined in mep-core.cpu.
31 (comment "64-bit coprocessor registers for rh coprocessor for core 1")
41 (comment "32-bit coprocessor registers for rh coprocessor for core 1")
51 (comment "Coprocessor control registers for rh coprocessor for core 1")
140 ; new nops are defined in new coprocessor insn sets.
177 (dncp116i movcp16 "16-bit coprocessor move insn"
185 (dncp116i movcp16a "16-bit coprocessor move insn"
193 (dncp116i movcp16b "16-bit coprocessor move insn"
201 (dncp116i cp16nop "16-bit coprocessor nop"
[all …]
H A Diq2000m.cpu121 ; Architectural and coprocessor instructions.
182 (dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
188 (dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
194 (dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
200 (dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
216 (dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
222 (dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
228 (dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
234 (dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
324 (dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
[all …]
H A Dmep-c5.cpu106 (dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
116 (dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
125 (dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
135 (dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
145 (dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
154 (dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
164 (dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
174 (dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
H A Dmep-fmax.cpu25 ; specified below for each ME_MODULE using this coprocessor.
26 ; This coprocessor requires only the 32 bit insns in the core.
104 ; Given a coprocessor register number N, expand to a
109 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
112 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
129 …TE: This exists solely for the purpose of providing the proper register names for this coprocessor.
132 ; the core and the coprocessor but use parse/print handlers which reference the hardware table
H A Dmep-core.cpu60 (comment "MeP coprocessor instruction set")
68 (comment "MeP coprocessor instruction set")
76 (comment "MeP coprocessor instruction set")
84 (comment "MeP coprocessor instruction set")
273 (comment "64-bit coprocessor registers")
282 (comment "64-bit coprocessor registers, pending writes")
290 (comment "32-bit coprocessor registers")
298 ;; Given a coprocessor control register number N, expand to a
509 ; These are all for the coprocessor opcodes
573 (comment "coprocessor code")
[all …]
/netbsd-src/sys/arch/arm/arm/
H A Dundefined.c309 int coprocessor; in undefinedinstruction() local
388 coprocessor = THUMB_UNKNOWN_HANDLER; in undefinedinstruction()
407 coprocessor = (fault_instruction >> 8) & 0x0f; in undefinedinstruction()
410 coprocessor = THUMB_UNKNOWN_HANDLER; in undefinedinstruction()
413 coprocessor = CORE_UNKNOWN_HANDLER; in undefinedinstruction()
429 LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link) { in undefinedinstruction()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dunspecs.md229 VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
230 VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
231 VUNSPEC_LDC ; Represent the coprocessor ldc instruction.
232 VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction.
233 VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction.
234 VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction.
235 VUNSPEC_STC ; Represent the coprocessor stc instruction.
236 VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
237 VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
238 VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dunspecs.md228 VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
229 VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
230 VUNSPEC_LDC ; Represent the coprocessor ldc instruction.
231 VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction.
232 VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction.
233 VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction.
234 VUNSPEC_STC ; Represent the coprocessor stc instruction.
235 VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
236 VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
237 VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
[all …]

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