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Searched refs:constrainRegClass (Results 1 – 25 of 36) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp368 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
371 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); in AssignSlot()
374 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); in AssignSlot()
377 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); in AssignSlot()
H A DSILowerI1Copies.cpp481 MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass); in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() function
85 MachineRegisterInfo::constrainRegClass(Register Reg, in constrainRegClass() function in MachineRegisterInfo
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
109 if (!::constrainRegClass( in constrainRegAttrs()
H A DTargetInstrInfo.cpp851 MRI.constrainRegClass(RegA, RC); in reassociateOps()
853 MRI.constrainRegClass(RegB, RC); in reassociateOps()
855 MRI.constrainRegClass(RegX, RC); in reassociateOps()
857 MRI.constrainRegClass(RegY, RC); in reassociateOps()
859 MRI.constrainRegClass(RegC, RC); in reassociateOps()
H A DOptimizePHIs.cpp181 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
H A DUnreachableBlockElim.cpp183 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
H A DMachineLoopUtils.cpp67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg())); in PeelSingleBlockLoop()
H A DTailDuplicator.cpp250 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate()
427 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
H A DModuloSchedule.cpp1188 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1235 MRI.constrainRegClass(MI.getOperand(1).getReg(), in EliminateDeadPhis()
1484 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue())); in phi()
1494 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
H A DTwoAddressInstructionPass.cpp1343 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands()
1453 MRI->constrainRegClass(RegA, RC); in processTiedPairs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp104 if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) { in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp643 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
H A DAArch64InstrInfo.cpp701 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
707 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
747 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
751 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
755 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
758 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
786 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
787 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
1213 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
3630 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
[all …]
H A DAArch64RegisterInfo.cpp559 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp387 MRI->constrainRegClass(StartReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
388 MRI->constrainRegClass(PhiReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
389 MRI->constrainRegClass(DecReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
502 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
H A DThumb2InstrInfo.cpp193 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
234 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
713 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
H A DA15SDOptimizer.cpp640 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
H A DARMLoadStoreOptimizer.cpp2436 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2437 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2787 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
2790 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
H A DARMBaseRegisterInfo.cpp661 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp237 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
H A DPPCRegisterInfo.cpp1464 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
1492 MRI.constrainRegClass(BaseReg, in resolveFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp326 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
456 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp138 return MRI.constrainRegClass(Reg, &RC); in constrainGenericRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp509 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h694 const TargetRegisterClass *constrainRegClass(Register Reg,

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