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Searched refs:clock_req (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c774 struct pp_display_clock_request clock_req; in pp_nv_set_hard_min_dcefclk_by_freq() local
779 clock_req.clock_type = amd_pp_dcef_clock; in pp_nv_set_hard_min_dcefclk_by_freq()
780 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_dcefclk_by_freq()
785 if (smu_display_clock_voltage_request(smu, &clock_req)) in pp_nv_set_hard_min_dcefclk_by_freq()
796 struct pp_display_clock_request clock_req; in pp_nv_set_hard_min_uclk_by_freq() local
801 clock_req.clock_type = amd_pp_mem_clock; in pp_nv_set_hard_min_uclk_by_freq()
802 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_uclk_by_freq()
807 if (smu_display_clock_voltage_request(smu, &clock_req)) in pp_nv_set_hard_min_uclk_by_freq()
832 struct pp_display_clock_request clock_req; in pp_nv_set_voltage_by_freq() local
839 clock_req.clock_type = amd_pp_disp_clock; in pp_nv_set_voltage_by_freq()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu10_hwmgr.c64 struct pp_display_clock_request *clock_req) in smu10_display_clock_voltage_request() argument
67 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu10_display_clock_voltage_request()
68 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu10_display_clock_voltage_request()
203 struct pp_display_clock_request clock_req; in smu10_set_clock_limit() local
206 clock_req.clock_type = amd_pp_dcf_clock; in smu10_set_clock_limit()
207 clock_req.clock_freq_in_khz = clocks.dcefClock * 10; in smu10_set_clock_limit()
209 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), in smu10_set_clock_limit()
H A Damdgpu_vega12_hwmgr.c1436 struct pp_display_clock_request *clock_req) in vega12_display_clock_voltage_request() argument
1440 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request()
1441 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega12_display_clock_voltage_request()
1482 struct pp_display_clock_request clock_req; in vega12_notify_smc_display_config_after_ps_adjustment() local
1496 clock_req.clock_type = amd_pp_dcef_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1497 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; in vega12_notify_smc_display_config_after_ps_adjustment()
1498 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { in vega12_notify_smc_display_config_after_ps_adjustment()
H A Damdgpu_vega20_hwmgr.c2252 struct pp_display_clock_request *clock_req) in vega20_display_clock_voltage_request() argument
2256 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega20_display_clock_voltage_request()
2257 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega20_display_clock_voltage_request()
2307 struct pp_display_clock_request clock_req; in vega20_notify_smc_display_config_after_ps_adjustment() local
2315 clock_req.clock_type = amd_pp_dcef_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
2316 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()
2317 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { in vega20_notify_smc_display_config_after_ps_adjustment()
H A Damdgpu_vega10_hwmgr.c3907 struct pp_display_clock_request *clock_req) in vega10_display_clock_voltage_request() argument
3910 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega10_display_clock_voltage_request()
3911 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega10_display_clock_voltage_request()
3976 struct pp_display_clock_request clock_req; in vega10_notify_smc_display_config_after_ps_adjustment() local
3995 clock_req.clock_type = amd_pp_dcef_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
3996 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; in vega10_notify_smc_display_config_after_ps_adjustment()
3997 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { in vega10_notify_smc_display_config_after_ps_adjustment()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dsmu_v11_0.h221 *clock_req);
H A Damdgpu_smu.h542 *clock_req);
635 struct pp_display_clock_request *clock_req);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_navi10_ppt.c1461 struct pp_display_clock_request clock_req; in navi10_notify_smc_display_config() local
1469 clock_req.clock_type = amd_pp_dcef_clock; in navi10_notify_smc_display_config()
1470 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_display_config()
1472 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); in navi10_notify_smc_display_config()
H A Damdgpu_smu_v11_0.c1317 *clock_req) in smu_v11_0_display_clock_voltage_request()
1319 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request()
1322 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu_v11_0_display_clock_voltage_request()
H A Damdgpu_vega20_ppt.c2243 struct pp_display_clock_request clock_req; in vega20_notify_smc_display_config() local
2251 clock_req.clock_type = amd_pp_dcef_clock; in vega20_notify_smc_display_config()
2252 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in vega20_notify_smc_display_config()
2253 if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) { in vega20_notify_smc_display_config()
H A Damdgpu_smu.c2424 struct pp_display_clock_request *clock_req) in smu_display_clock_voltage_request() argument
2431 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); in smu_display_clock_voltage_request()