Home
last modified time | relevance | path

Searched refs:clock_ranges (Results 1 – 14 of 14) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_renoir_ppt.c768 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges) in renoir_set_watermarks_table() argument
774 if (!table || !clock_ranges) in renoir_set_watermarks_table()
777 if (clock_ranges->num_wm_dmif_sets > 4 || in renoir_set_watermarks_table()
778 clock_ranges->num_wm_mcif_sets > 4) in renoir_set_watermarks_table()
782 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in renoir_set_watermarks_table()
785 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz)); in renoir_set_watermarks_table()
788 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz)); in renoir_set_watermarks_table()
791 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz)); in renoir_set_watermarks_table()
794 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz)); in renoir_set_watermarks_table()
796 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; in renoir_set_watermarks_table()
[all …]
H A Damdgpu_navi10_ppt.c1502 *clock_ranges) in navi10_set_watermarks_table()
1507 if (!table || !clock_ranges) in navi10_set_watermarks_table()
1510 if (clock_ranges->num_wm_dmif_sets > 4 || in navi10_set_watermarks_table()
1511 clock_ranges->num_wm_mcif_sets > 4) in navi10_set_watermarks_table()
1514 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in navi10_set_watermarks_table()
1517 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / in navi10_set_watermarks_table()
1521 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / in navi10_set_watermarks_table()
1525 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / in navi10_set_watermarks_table()
1529 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / in navi10_set_watermarks_table()
1532 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; in navi10_set_watermarks_table()
[all …]
H A Damdgpu_vega20_ppt.c3045 *clock_ranges) in vega20_set_watermarks_table()
3050 if (!table || !clock_ranges) in vega20_set_watermarks_table()
3053 if (clock_ranges->num_wm_dmif_sets > 4 || in vega20_set_watermarks_table()
3054 clock_ranges->num_wm_mcif_sets > 4) in vega20_set_watermarks_table()
3057 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in vega20_set_watermarks_table()
3060 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / in vega20_set_watermarks_table()
3064 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / in vega20_set_watermarks_table()
3068 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / in vega20_set_watermarks_table()
3072 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / in vega20_set_watermarks_table()
3075 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; in vega20_set_watermarks_table()
[all …]
H A Dsmu_internal.h182 #define smu_set_watermarks_table(smu, tab, clock_ranges) \ argument
183 …s->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
H A Damdgpu_amd_powerplay.c1185 void *clock_ranges) in pp_set_watermarks_for_clocks_ranges() argument
1190 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) in pp_set_watermarks_for_clocks_ranges()
1195 clock_ranges); in pp_set_watermarks_for_clocks_ranges()
H A Damdgpu_smu.c2009 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges) in smu_set_watermarks_for_clock_ranges() argument
2021 smu_set_watermarks_table(smu, table, clock_ranges); in smu_set_watermarks_for_clock_ranges()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_hardwaremanager.c465 void *clock_ranges) in phm_set_watermarks_for_clocks_ranges() argument
473 clock_ranges); in phm_set_watermarks_for_clocks_ranges()
H A Damdgpu_smu10_hwmgr.c1161 void *clock_ranges) in smu10_set_watermarks_for_clocks_ranges() argument
1164 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in smu10_set_watermarks_for_clocks_ranges()
H A Damdgpu_vega12_hwmgr.c1868 void *clock_ranges) in vega12_set_watermarks_for_clocks_ranges() argument
1872 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega12_set_watermarks_for_clocks_ranges()
H A Damdgpu_vega20_hwmgr.c2898 void *clock_ranges) in vega20_set_watermarks_for_clocks_ranges() argument
2902 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega20_set_watermarks_for_clocks_ranges()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/
H A Dkgd_pp_interface.h308 void *clock_ranges);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Damdgpu_smu.h475 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
688 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
H A Dhardwaremanager.h461 void *clock_ranges);
H A Dhwmgr.h311 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);