Searched refs:clock_limits (Results 1 – 8 of 8) sorted by relevance
233 .clock_limits = {2696 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()2697 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()2719 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; in dcn20_calculate_wm()2720 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn20_calculate_wm()2725 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; in dcn20_calculate_wm()2726 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; in dcn20_calculate_wm()2739 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()2740 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; in dcn20_calculate_wm()2752 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()[all …]
244 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()247 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()248 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()249 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()250 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()262 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()263 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()264 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()265 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()266 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()[all …]
115 struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; member
168 .clock_limits = {991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()1351 dcn2_1_soc.clock_limits[i].state = i; in update_bw_bounding_box()1352 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in update_bw_bounding_box()1353 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in update_bw_bounding_box()1354 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in update_bw_bounding_box()1355 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in update_bw_bounding_box()1357 dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1]; in update_bw_bounding_box()
81 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
1325 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1265 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1644 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()