Home
last modified time | relevance | path

Searched refs:clk_table (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega10_processpptables.c580 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
589 clk_table = kzalloc(table_size, GFP_KERNEL); in get_socclk_voltage_dependency_table()
591 if (!clk_table) in get_socclk_voltage_dependency_table()
594 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
597 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
599 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
603 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
654 *clk_table; in get_gfxclk_voltage_dependency_table() local
664 clk_table = kzalloc(table_size, GFP_KERNEL); in get_gfxclk_voltage_dependency_table()
666 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
H A Damdgpu_process_pptables_v1_0.c322 struct phm_clock_array **clk_table, in get_valid_clk() argument
349 *clk_table = table; in get_valid_clk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_renoir_ppt.c233 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in renoir_get_dpm_clk_limited() local
235 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
238 GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); in renoir_get_dpm_clk_limited()
248 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in renoir_print_clk_levels() local
251 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_print_clk_levels()
305 GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); in renoir_print_clk_levels()
614 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in renoir_force_clk_levels() local
642 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq); in renoir_force_clk_levels()
643 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq); in renoir_force_clk_levels()
653 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq); in renoir_force_clk_levels()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
H A Damdgpu_rn_clk_mgr.c436 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
438 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
515 .clk_table = {
663 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
665 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
666 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
669 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
678 if (i >= bw_params->clk_table.num_entries) { in rn_clk_mgr_helper_populate_bw_params()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_resource.c1099 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
1342 struct clk_limit_table *clk_table = &bw_params->clk_table; in update_bw_bounding_box() local
1349 for (i = 0; i < clk_table->num_entries; i++) { in update_bw_bounding_box()
1352 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in update_bw_bounding_box()
1353 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in update_bw_bounding_box()
1354 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in update_bw_bounding_box()
1355 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in update_bw_bounding_box()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h153 struct clk_limit_table clk_table; member