| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| H A D | amdgpu_dce80_resource.c | 342 #define clk_src_regs(id)\ macro
348 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
349 clk_src_regs(0),
350 clk_src_regs(1),
351 clk_src_regs(2)
962 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); in dce80_construct()
964 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); in dce80_construct()
966 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); in dce80_construct()
971 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); in dce80_construct()
974 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); in dce80_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| H A D | amdgpu_dce120_resource.c | 403 #define clk_src_regs(index, id)\ macro
408 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
409 clk_src_regs(0, A),
410 clk_src_regs(1, B),
411 clk_src_regs(2, C),
412 clk_src_regs(3, D),
413 clk_src_regs(4, E),
414 clk_src_regs(5, F)
1070 &clk_src_regs[0], false); in dce120_resource_construct()
1074 &clk_src_regs[1], false); in dce120_resource_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| H A D | amdgpu_dce112_resource.c | 357 #define clk_src_regs(index, id)\ macro
362 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
363 clk_src_regs(0, A),
364 clk_src_regs(1, B),
365 clk_src_regs(2, C),
366 clk_src_regs(3, D),
367 clk_src_regs(4, E),
368 clk_src_regs(5, F)
1226 &clk_src_regs[0], false); in dce112_resource_construct()
1231 &clk_src_regs[1], false); in dce112_resource_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| H A D | amdgpu_dce100_resource.c | 316 #define clk_src_regs(id)\ macro
321 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
322 clk_src_regs(0),
323 clk_src_regs(1),
324 clk_src_regs(2)
980 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); in dce100_resource_construct()
982 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); in dce100_resource_construct()
984 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); in dce100_resource_construct()
989 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); in dce100_resource_construct()
992 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); in dce100_resource_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_resource.c | 511 #define clk_src_regs(index, pllid)\ macro
516 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
517 clk_src_regs(0, A),
518 clk_src_regs(1, B),
519 clk_src_regs(2, C),
520 clk_src_regs(3, D)
1372 &clk_src_regs[0], false); in dcn10_resource_construct()
1376 &clk_src_regs[1], false); in dcn10_resource_construct()
1380 &clk_src_regs[2], false); in dcn10_resource_construct()
1386 &clk_src_regs[3], false); in dcn10_resource_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| H A D | amdgpu_dcn21_resource.c | 336 #define clk_src_regs(index, pllid)\ macro
341 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
342 clk_src_regs(0, A),
343 clk_src_regs(1, B),
344 clk_src_regs(2, C),
345 clk_src_regs(3, D),
346 clk_src_regs(4, E),
1723 &clk_src_regs[0], false); in dcn21_resource_construct()
1727 &clk_src_regs[1], false); in dcn21_resource_construct()
1731 &clk_src_regs[2], false); in dcn21_resource_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | amdgpu_dce110_resource.c | 354 #define clk_src_regs(id)\ macro
359 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
360 clk_src_regs(0),
361 clk_src_regs(1),
362 clk_src_regs(2)
1362 &clk_src_regs[0], false); in dce110_resource_construct()
1365 &clk_src_regs[1], false); in dce110_resource_construct()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_resource.c | 430 #define clk_src_regs(index, pllid)\ macro
435 static const struct dce110_clk_src_regs clk_src_regs[] = { variable
436 clk_src_regs(0, A),
437 clk_src_regs(1, B),
438 clk_src_regs(2, C),
439 clk_src_regs(3, D),
440 clk_src_regs(4, E),
441 clk_src_regs(5, F)
3552 &clk_src_regs[0], false); in dcn20_resource_construct()
3556 &clk_src_regs[1], false); in dcn20_resource_construct()
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