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Searched refs:clk_mgr (Results 1 – 25 of 42) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
H A Damdgpu_dcn20_clk_mgr.c48 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
51 (clk_mgr->regs->reg)
108 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in dcn20_update_clocks_update_dpp_dto() argument
113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
114 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
123 …prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_kh… in dcn20_update_clocks_update_dpp_dto()
126 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
127 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
132 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) in dcn20_update_clocks_update_dentist() argument
135 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
[all …]
H A Ddcn20_clk_mgr.h31 void dcn2_update_clocks(struct clk_mgr *dccg,
35 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
38 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
41 void dcn2_init_clocks(struct clk_mgr *clk_mgr);
44 struct clk_mgr_internal *clk_mgr,
50 void dcn2_get_clock(struct clk_mgr *clk_mgr,
55 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);
57 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A Damdgpu_rv1_clk_mgr.c42 void rv1_init_clocks(struct clk_mgr *clk_mgr) in rv1_init_clocks() argument
44 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
47 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_c… in rv1_determine_dppclk_threshold() argument
50 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
52 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
82 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
93 static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc *dc, struct dc_clo… in ramp_up_dispclk_with_dpp() argument
96 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); in ramp_up_dispclk_with_dpp()
101 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); in ramp_up_dispclk_with_dpp()
102 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp()
[all …]
H A Damdgpu_rv1_clk_mgr_vbios_smu.c76 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsign… in rv1_vbios_smu_send_msg_with_param() argument
93 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rv1_vbios_smu_set_dispclk() argument
96 struct dc *dc = clk_mgr->base.ctx->dc; in rv1_vbios_smu_set_dispclk()
101 clk_mgr, in rv1_vbios_smu_set_dispclk()
110 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) in rv1_vbios_smu_set_dispclk()
119 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rv1_vbios_smu_set_dprefclk() argument
124 clk_mgr, in rv1_vbios_smu_set_dprefclk()
126 clk_mgr->base.dprefclk_khz / 1000); in rv1_vbios_smu_set_dprefclk()
H A Damdgpu_rv2_clk_mgr.c42 void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_… in rv2_clk_mgr_construct() argument
45 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
47 clk_mgr->funcs = &rv2_clk_internal_funcs; in rv2_clk_mgr_construct()
H A Drv1_clk_mgr_vbios_smu.h31 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
32 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
H A Drv1_clk_mgr_clk.c57 …egisters(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) in rv1_dump_clk_registers()
59 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_dump_clk_registers() local
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
H A Damdgpu_rn_clk_mgr_vbios_smu.c61 int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigne… in rn_vbios_smu_send_msg_with_param() argument
78 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_get_smu_version() argument
81 clk_mgr, in rn_vbios_smu_get_smu_version()
87 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rn_vbios_smu_set_dispclk() argument
90 struct dc *dc = clk_mgr->base.ctx->dc; in rn_vbios_smu_set_dispclk()
95 clk_mgr, in rn_vbios_smu_set_dispclk()
101 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) in rn_vbios_smu_set_dispclk()
110 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_set_dprefclk() argument
115 clk_mgr, in rn_vbios_smu_set_dprefclk()
117 clk_mgr->base.dprefclk_khz / 1000); in rn_vbios_smu_set_dprefclk()
[all …]
H A Damdgpu_rn_clk_mgr.c101 void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks()
105 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_update_clocks() local
129 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); in rn_update_clocks()
137 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE); in rn_update_clocks()
145 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); in rn_update_clocks()
150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in rn_update_clocks()
156 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in rn_update_clocks()
165 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in rn_update_clocks()
166 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in rn_update_clocks()
174 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in rn_update_clocks()
[all …]
H A Drn_clk_mgr_vbios_smu.h31 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
32 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
33 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
34 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
35 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d…
36 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
37 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
38 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
39 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
40 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/
H A Damdgpu_clk_mgr.c71 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_exit_optimized_pwr_state() argument
79 clk_mgr->psr_allow_active_cache = edp_link->psr_allow_active; in clk_mgr_exit_optimized_pwr_state()
85 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_optimize_pwr_state() argument
90 dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false); in clk_mgr_optimize_pwr_state()
97 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create()
101 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
103 if (clk_mgr == NULL) { in dc_clk_mgr_create()
111 dce_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
114 dce110_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
119 dce_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
[all …]
H A DMakefile26 CLK_MGR = clk_mgr.o
28 AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
38 AMD_DAL_CLK_MGR_DCE100 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce100/,$(CLK_MGR_DCE100))
47 AMD_DAL_CLK_MGR_DCE110 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce110/,$(CLK_MGR_DCE110))
55 AMD_DAL_CLK_MGR_DCE112 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce112/,$(CLK_MGR_DCE112))
63 AMD_DAL_CLK_MGR_DCE120 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce120/,$(CLK_MGR_DCE120))
72 AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))
81 AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DCN20))
93 CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
96 AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c53 clk_mgr->ctx->logger
153 static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce_get_dp_ref_freq_khz() argument
155 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_get_dp_ref_freq_khz()
179 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce12_get_dp_ref_freq_khz() argument
181 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce12_get_dp_ref_freq_khz()
219 struct clk_mgr *clk_mgr, in dce_get_required_clocks_state() argument
222 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_get_required_clocks_state()
252 struct clk_mgr *clk_mgr, in dce_set_clock() argument
255 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_set_clock()
257 struct dc_bios *bp = clk_mgr->ctx->dc_bios; in dce_set_clock()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h170 void (*update_clocks)(struct clk_mgr *clk_mgr,
174 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
176 void (*init_clocks)(struct clk_mgr *clk_mgr);
178 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
179 void (*get_clock)(struct clk_mgr *clk_mgr,
186 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
189 struct clk_mgr { struct
203 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … argument
205 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
207 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
[all …]
H A Dclk_mgr_internal.h71 #define TO_CLK_MGR_INTERNAL(clk_mgr)\ argument
72 container_of(clk_mgr, struct clk_mgr_internal, base)
75 clk_mgr->base.ctx
77 clk_mgr->ctx->logger
198 struct clk_mgr base;
268 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
269 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
H A Damdgpu_dce_clk_mgr.c52 (clk_mgr->regs->reg)
56 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
134 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz()
136 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz() local
155 * clk_mgr->base.dentist_vco_freq_khz) / target_div; in dce_get_dp_ref_freq_khz()
157 return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); in dce_get_dp_ref_freq_khz()
160 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz()
200 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state()
235 struct clk_mgr *clk_mgr_base, in dce_set_clock()
400 static void dce_update_clocks(struct clk_mgr *clk_mgr_base, in dce_update_clocks()
[all …]
H A Ddce_clk_mgr.h36 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
38 struct clk_mgr *clk_mgr_base,
50 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
53 struct clk_mgr *clk_mgr_base,
57 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
H A Damdgpu_dce112_clk_mgr.c75 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock()
130 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) in dce112_set_dispclk() argument
133 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_dispclk()
134 struct dc *dc = clk_mgr->base.ctx->dc; in dce112_set_dispclk()
143 clk_mgr->base.dentist_vco_freq_khz / 62); in dce112_set_dispclk()
157 clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce112_set_dispclk()
162 if (clk_mgr->dfs_bypass_disp_clk != actual_clock) in dce112_set_dispclk()
168 clk_mgr->dfs_bypass_disp_clk = actual_clock; in dce112_set_dispclk()
173 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dce112_set_dprefclk() argument
176 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_dprefclk()
[all …]
H A Ddce112_clk_mgr.h34 struct clk_mgr_internal *clk_mgr);
37 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
38 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
39 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
H A Damdgpu_dce120_clk_mgr.c89 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks()
133 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce120_clk_mgr_construct() argument
135 dce_clk_mgr_construct(ctx, clk_mgr); in dce120_clk_mgr_construct()
137 memcpy(clk_mgr->max_clks_by_state, in dce120_clk_mgr_construct()
141 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()
142 clk_mgr->base.funcs = &dce120_funcs; in dce120_clk_mgr_construct()
145 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce121_clk_mgr_construct() argument
147 dce120_clk_mgr_construct(ctx, clk_mgr); in dce121_clk_mgr_construct()
148 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
155 dce121_clock_patch_xgmi_ss_info(clk_mgr); in dce121_clk_mgr_construct()
H A Ddce120_clk_mgr.h31 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
32 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
H A Damdgpu_dce110_clk_mgr.c235 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
253 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks()
287 struct clk_mgr_internal *clk_mgr) in dce110_clk_mgr_construct() argument
289 dce_clk_mgr_construct(ctx, clk_mgr); in dce110_clk_mgr_construct()
291 memcpy(clk_mgr->max_clks_by_state, in dce110_clk_mgr_construct()
295 clk_mgr->regs = &disp_clk_regs; in dce110_clk_mgr_construct()
296 clk_mgr->clk_mgr_shift = &disp_clk_shift; in dce110_clk_mgr_construct()
297 clk_mgr->clk_mgr_mask = &disp_clk_mask; in dce110_clk_mgr_construct()
298 clk_mgr->base.funcs = &dce110_funcs; in dce110_clk_mgr_construct()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
H A Damdgpu_dce100_hw_sequencer.c119 dc->clk_mgr->funcs->update_clocks( in dce100_prepare_bandwidth()
120 dc->clk_mgr, in dce100_prepare_bandwidth()
131 dc->clk_mgr->funcs->update_clocks( in dce100_optimize_bandwidth()
132 dc->clk_mgr, in dce100_optimize_bandwidth()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_hwseq.c104 dc->clk_mgr->funcs->update_clocks( in dcn21_exit_optimized_pwr_state()
105 dc->clk_mgr, in dcn21_exit_optimized_pwr_state()
114 dc->clk_mgr->funcs->update_clocks( in dcn21_optimize_pwr_state()
115 dc->clk_mgr, in dcn21_optimize_pwr_state()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hw_sequencer.c1248 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn10_init_hw()
1249 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn10_init_hw()
1366 if (dc->clk_mgr->funcs->notify_wm_ranges) in dcn10_init_hw()
1367 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); in dcn10_init_hw()
2251 dc->clk_mgr->clks.dispclk_khz / 2; in dcn10_update_dchubp_dpp()
2264 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? in dcn10_update_dchubp_dpp()
2265 dc->clk_mgr->clks.dispclk_khz / 2 : in dcn10_update_dchubp_dpp()
2266 dc->clk_mgr->clks.dispclk_khz; in dcn10_update_dchubp_dpp()
2658 dc->clk_mgr->funcs->update_clocks( in dcn10_prepare_bandwidth()
2659 dc->clk_mgr, in dcn10_prepare_bandwidth()
[all …]

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