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Searched refs:cdclk (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_cdclk.c65 cdclk_state->cdclk = 133333; in fixed_133mhz_get_cdclk()
71 cdclk_state->cdclk = 200000; in fixed_200mhz_get_cdclk()
77 cdclk_state->cdclk = 266667; in fixed_266mhz_get_cdclk()
83 cdclk_state->cdclk = 333333; in fixed_333mhz_get_cdclk()
89 cdclk_state->cdclk = 400000; in fixed_400mhz_get_cdclk()
95 cdclk_state->cdclk = 450000; in fixed_450mhz_get_cdclk()
110 cdclk_state->cdclk = 133333; in i85x_get_cdclk()
124 cdclk_state->cdclk = 200000; in i85x_get_cdclk()
127 cdclk_state->cdclk = 250000; in i85x_get_cdclk()
130 cdclk_state->cdclk = 133333; in i85x_get_cdclk()
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H A Dintel_atomic.c513 memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical)); in intel_atomic_state_clear()
514 memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual)); in intel_atomic_state_clear()
515 state->cdclk.pipe = INVALID_PIPE; in intel_atomic_state_clear()
H A Dintel_atomic_plane.c190 if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) { in intel_plane_calc_min_cdclk()
194 dev_priv->cdclk.logical.cdclk); in intel_plane_calc_min_cdclk()
H A Dintel_cdclk.h22 u32 cdclk; member
H A Dintel_audio.c825 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; in glk_force_audio_cdclk()
826 to_intel_atomic_state(state)->cdclk.force_min_cdclk = in glk_force_audio_cdclk()
930 return dev_priv->cdclk.hw.cdclk; in i915_audio_component_get_cdclk_freq()
H A Dintel_dpll_mgr.c2268 int ref_clock = dev_priv->cdclk.hw.ref; in cnl_hdmi_pll_ref_clock()
2565 dev_priv->cdclk.hw.ref == 24000 ? in icl_calc_dp_combo_pll()
2588 switch (dev_priv->cdclk.hw.ref) { in icl_calc_tbt_pll()
2590 MISSING_CASE(dev_priv->cdclk.hw.ref); in icl_calc_tbt_pll()
2601 switch (dev_priv->cdclk.hw.ref) { in icl_calc_tbt_pll()
2603 MISSING_CASE(dev_priv->cdclk.hw.ref); in icl_calc_tbt_pll()
2755 int refclk_khz = dev_priv->cdclk.hw.ref; in icl_calc_mg_pll_state()
3180 if (dev_priv->cdclk.hw.ref == 38400) { in mg_pll_get_hw_state()
H A Dintel_fbc.c761 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { in intel_fbc_can_activate()
H A Dintel_panel.c1488 clock = KHz(dev_priv->cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1506 clock = KHz(dev_priv->cdclk.hw.cdclk); in i965_hz_to_pwm()
H A Dintel_display.c7813 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100) in hsw_compute_ips_config()
14302 if (!state->cdclk.force_min_cdclk_changed) in intel_modeset_checks()
14303 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk; in intel_modeset_checks()
14307 state->cdclk.logical = dev_priv->cdclk.logical; in intel_modeset_checks()
14308 state->cdclk.actual = dev_priv->cdclk.actual; in intel_modeset_checks()
14703 any_ms |= state->cdclk.force_min_cdclk_changed; in intel_atomic_check()
14714 state->cdclk.logical = dev_priv->cdclk.logical; in intel_atomic_check()
15367 &state->cdclk.actual, in intel_atomic_commit_tail()
15368 &dev_priv->cdclk.actual, in intel_atomic_commit_tail()
15369 state->cdclk.pipe); in intel_atomic_commit_tail()
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H A Dintel_display_types.h482 } cdclk; member
H A Dintel_display_power.c1060 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); in gen9_disable_dc_states()
4676 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
H A Dintel_dp.c1255 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); in ilk_get_aux_clock_divider()
H A Dintel_ddi.c1461 ref_clock = dev_priv->cdclk.hw.ref; in icl_calc_mg_pll_link()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Ds3c64xx-pinctrl.dtsi334 i2s0_cdclk: i2s0-cdclk {
346 i2s1_cdclk: i2s1-cdclk {
360 i2s2_cdclk: i2s2-cdclk {
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Ddebugfs_gt_pm.c460 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); in frequency_show()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_drv.h288 u8 (*calc_voltage_level)(int cdclk);
895 unsigned int cdclk, vco, ref, bypass; member
1052 } cdclk; member
H A Dintel_pm.c2835 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) in hsw_compute_linetime_wm()
2844 intel_state->cdclk.logical.cdclk); in hsw_compute_linetime_wm()
H A Di915_debugfs.c1004 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); in i915_frequency_info()