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Searched refs:cacheline_size (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/dev/pci/
H A Dpciconf.c158 int cacheline_size; member
408 pb->cacheline_size = parent->cacheline_size; in query_bus()
1348 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << in configure_bus()
1547 int firstbus, int cacheline_size) in pci_configure_bus() argument
1556 pb->cacheline_size = cacheline_size; in pci_configure_bus()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
H A Dkfd_topology.h125 uint32_t cacheline_size; member
H A Dkfd_crat.c326 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
H A Dkfd_topology.c352 sysfs_show_32bit_prop(buffer, "cache_line_size", cache->cacheline_size); in kfd_cache_show()
/netbsd-src/sys/dev/marvell/
H A Dgtpci.c444 int cacheline_size) in gtpci_pci_config() argument
460 GTPCI_P2PC_BUSNUMBER(p2pc), cacheline_size); in gtpci_pci_config()
H A Dmvpex.c408 int cacheline_size) in mvpex_pci_config() argument
424 MVPEX_STAT_PEXBUSNUM(stat), cacheline_size); in mvpex_pci_config()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Dintel_pm.c567 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
575 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
583 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
591 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
599 .cacheline_size = I915_FIFO_LINE_SIZE,
607 .cacheline_size = I915_FIFO_LINE_SIZE,
615 .cacheline_size = I915_FIFO_LINE_SIZE,
623 .cacheline_size = I830_FIFO_LINE_SIZE,
631 .cacheline_size = I830_FIFO_LINE_SIZE,
639 .cacheline_size = I830_FIFO_LINE_SIZE,
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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_display_types.h1149 u8 cacheline_size; member