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/netbsd-src/sys/arch/arm/arm/
H A Dcpufunc_asm_arm8.S80 mcrne p15, 0, r0, c7, c7, 0 /* flush I+D cache */
86 mcrne p15, 0, r0, c8, c7, 0
89 mcrne p15, 0, r0, c7, c7, 0
103 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
108 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
111 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
120 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
125 mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
133 mcr p15, 0, r2, c7, c11, 1
135 mcr p15, 0, r2, c7, c11, 1
[all …]
H A Dcpufunc_asm_xscale.S122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
151 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
164 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
201 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
206 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
211 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
216 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
226 mcr p15, 0, r0, c7, c10, 1
[all …]
H A Dcpufunc_asm_sa1.S67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
75 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
109 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
114 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
119 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
124 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
129 mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
198 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
[all …]
H A Dcpufunc_asm_armv5_ec.S64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
65 2: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
67 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
71 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
110 mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */
112 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
[all …]
H A Dcpufunc_asm_arm11x6.S70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
105 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
106 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
110 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
111 mrc p15, 0, reg, c7, c10, 6;/* Read Cache Dirty Status Register */ \
114 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
[all …]
H A Dcpufunc_asm_armv6.S52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
53 mcrne p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain the write buffer */
59 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
85 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
86 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
104 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
[all …]
H A Dcpufunc_asm_arm11.S54 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
71 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
77 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
94 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
110 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
117 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
132 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
138 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
139 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
[all …]
H A Dcpufunc_asm_armv5.S56 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
79 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
80 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
131 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
[all …]
H A Dcpufunc_asm_arm9.S55 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
116 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
120 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
139 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
156 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
177 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
194 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
[all …]
H A Dcpufunc_asm_arm67.S53 mcrne p15, 0, r2, c7, c0, 0
62 mcrne p15, 0, r0, c7, c0, 0
85 mcr p15, 0, r0, c7, c0, 0
96 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
106 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
H A Dcpufunc_asm_arm7tdmi.S83 mcr p15, 0, r0, c8, c7, 0
88 mcr p15, 0, r0, c8, c7, 1
91 mcr p15, 0, r0, c8, c7, 1
102 mcr p15, 0, r0, c7, c7, 0
H A Dcpufunc_asm_armv7.S59 mcr p15, 0, r0, c8, c7, 0 @ flush the I+D
68 mcr p15, 0, r0, c8, c7, 2 @ flush I+D tlb all ASID
88 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
91 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
129 mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb
130 mcr p15, 0, r0, c7, c5, 6 @ branch predictor invalidate
142 mcr p15, 0, r0, c7, c1, 6 @ branch predictor invalidate, IS
159 mcr p15, 0, r0, c8, c7, 0 @ invalidate all I+D TLBs
194 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache line
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line
[all …]
H A Dcpufunc_asm_arm1136.S40 mcr p15, 0, r0, c7, c10, 2 /* clean data cache line (via index) */
41 mcr p15, 0, r0, c7, c10, 5 /* data memory barrier */
42 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
H A Dcpufunc_asm_sheeva.S78 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
120 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
162 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
198 mcr p15, 0, r0, c7, c5, 1
211 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
257 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
301 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
345 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
354 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
363 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
/netbsd-src/external/ibm-public/postfix/dist/src/global/
H A Dnamadr_list.in8 ${SHLIB_ENV} ${VALGRIND} ./namadr_list 2001:240:5c7:0:2d0:b7ff:fe88:2ca7 dummy 2001:240:5c7:0:2d0:b…
9 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:240:5c7:0:2d0:b7ff:fe88:2ca7]' dummy 2001:240:5c7:0:2…
10 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:240:5c7:0:2d0:b7ff:fe88:2ca7]' dummy 2001:240:5c7:0:2…
11 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:240:5c7:0:2d0:b7ff:fe88:2ca7]/64' dummy 2001:240:5c7:…
12 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:240:5c7::]/64' dummy 2001:240:5c7:0:2d0:b7ff:fe88:2ca8
13 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:240:5c7::]/64' dummy 2001:24:5c7:0:2d0:b7ff:fe88:2ca8
14 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:24:5c7:0:2d0:b7ff:fe88:2ca8]' dummy 2001:24:5c7:0:2d0…
15 ${SHLIB_ENV} ${VALGRIND} ./namadr_list '[2001:24:5c7:0:2d0:b7ff:fe88:2ca8]' dummy 2001:24:5c7:0:2d0…
H A Dnamadr_list.ref11 ./namadr_list: warning: 2001:240:5c7:0:2d0:b7ff:fe88:2ca7 is unavailable. unsupported dictionary ty…
12 ./namadr_list: warning: command line: 2001:240:5c7:0:2d0:b7ff:fe88:2ca7: table lookup problem
13 dummy/2001:240:5c7:0:2d0:b7ff:fe88:2ca7: ERROR
14 dummy/2001:240:5c7:0:2d0:b7ff:fe88:2ca7: YES
15 dummy/2001:240:5c7:0:2d0:b7ff:fe88:2ca8: NO
16 …e: non-null host address bits in "2001:240:5c7:0:2d0:b7ff:fe88:2ca7/64", perhaps you should use "2…
17 dummy/2001:240:5c7:0:2d0:b7ff:fe88:2ca8: ERROR
18 dummy/2001:240:5c7:0:2d0:b7ff:fe88:2ca8: YES
19 dummy/2001:24:5c7:0:2d0:b7ff:fe88:2ca8: NO
20 dummy/2001:24:5c7:0:2d0:b7ff:fe88:2ca8: YES
[all …]
/netbsd-src/sys/arch/acorn32/stand/boot32/
H A Dstart.S80 mcreq p15, 0, r0, c7, c0, 0 /* flush v3 ID cache */
81 mcrne p15, 0, r0, c7, c7, 0 /* flush v4 ID cache */
82 mcrne p15, 0, r0, c7, c10, 4 /* drain WB (v4) */
96 /*1*/ mcrne p15, 0, r1, c7, c5, 0 /* write zero in ARMv4 MMU disable */
135 mcreq p15, 0, r0, c7, c0, 0 /* flush v3 ID cache */
136 mcrne p15, 0, r0, c7, c7, 0 /* flush v4 ID cache */
141 mcrne p15, 0, r0, c7, c10, 4 /* drain WB (v4) */
/netbsd-src/external/ibm-public/postfix/dist/src/util/
H A Ddict_cidr.map36 2001:240:5c7:0:2d0:b7ff:fe88:2ca7 match 2001:240:5c7:0:2d0:b7ff:fe88:2ca7
37 2001:240:5c7::/64 match netblock 2001:240:5c7::/64
H A Ddict_cidr.ref32 > get 2001:240:5c7:0:2d0:b7ff:fe88:2ca7
33 2001:240:5c7:0:2d0:b7ff:fe88:2ca7=match 2001:240:5c7:0:2d0:b7ff:fe88:2ca7
34 > get 2001:240:5c7:0:2d0:b7ff:febe:ca9f
35 2001:240:5c7:0:2d0:b7ff:febe:ca9f=match netblock 2001:240:5c7::/64
/netbsd-src/sys/arch/evbarm/ixm1200/
H A Dixm1200_start.S87 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */
88 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */
91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
154 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
/netbsd-src/external/mit/isl/dist/test_inputs/codegen/omega/
H A Dlefur04-0.c7 …c7 = max(max(max(max(500 * c5 + 2, c6), 1000 * c0 - c6), 1000 * c3 - 2 * c6 + 2), 500 * c1 + (c6 +… variable
8 s0(c0, c1, c2, c3, c2 / 3, c5, c6, c7);
/netbsd-src/sys/arch/evbarm/viper/
H A Dviper_start.S178 mcr p15, 0, r3, c7, c10, 2
184 mcr p15, 0, r6, c7, c10, 4
227 mcr p15, 0, r3, c7, c10, 2
233 mcr p15, 0, r6, c7, c10, 4
236 mcr p15, 0, r0, c8, c7, 0
/netbsd-src/sys/arch/hpc/stand/hpcboot/arm/
H A Darm.asm88 ; c7 (CRn) Cache Control Register
91 mcr p15, 0, r0, c7, c5, 0
112 ; c7 (CRn) Cache Control Register
115 mcr p15, 0, r0, c7, c6, 0
129 mcr p15, 0, r0, c7, c6, 0
140 ; c7 (CRn) Cache Control Register
143 mcr p15, 0, r0, c7, c10, 4
152 mcr p15, 0, r0, c8, c7, 0
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/whrlpool/
H A Dwp_block.c175 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7 argument
186 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ argument
187 c7,c0,c1,c2,c3,c4,c5,c6, \
188 c6,c7,c0,c1,c2,c3,c4,c5, \
189 c5,c6,c7,c0,c1,c2,c3,c4, \
190 c4,c5,c6,c7,c0,c1,c2,c3, \
191 c3,c4,c5,c6,c7,c0,c1,c2, \
192 c2,c3,c4,c5,c6,c7,c0,c1, \
193 c1,c2,c3,c4,c5,c6,c7,c0
205 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ argument
[all …]
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/whrlpool/
H A Dwp_block.c181 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7 argument
192 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ argument
193 c7,c0,c1,c2,c3,c4,c5,c6, \
194 c6,c7,c0,c1,c2,c3,c4,c5, \
195 c5,c6,c7,c0,c1,c2,c3,c4, \
196 c4,c5,c6,c7,c0,c1,c2,c3, \
197 c3,c4,c5,c6,c7,c0,c1,c2, \
198 c2,c3,c4,c5,c6,c7,c0,c1, \
199 c1,c2,c3,c4,c5,c6,c7,c0
211 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ argument
[all …]

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