| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1096 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); in narrowScalar()
3107 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); in lower()
3569 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, in fewerElementsVectorSelect()
4501 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); in narrowScalarShift()
4502 auto Hi = MIRBuilder.buildSelect( in narrowScalarShift()
4503 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); in narrowScalarShift()
4529 auto Lo = MIRBuilder.buildSelect( in narrowScalarShift()
4530 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); in narrowScalarShift()
4532 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); in narrowScalarShift()
5111 auto Select = MIRBuilder.buildSelect(NarrowTy, in narrowScalarSelect()
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| H A D | MachineIRBuilder.cpp | 764 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res, in buildSelect() function in MachineIRBuilder
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| H A D | IRTranslator.cpp | 1420 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1850 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1880 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull); in legalizeAddrSpaceCast()
1907 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
1933 auto Add = B.buildSelect(S64, And, One, Zero); in legalizeFceil()
2013 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
2014 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
2640 CorrectedFract = B.buildSelect(S64, IsNan, ModSrc, Min, Flags).getReg(0); in legalizeFFloor()
2825 Q = B.buildSelect(S32, Cond, B.buildAdd(S32, Q, One), Q); in legalizeUDIV_UREM32Impl()
2826 R = B.buildSelect(S32, Cond, B.buildSub(S32, R, Y), R); in legalizeUDIV_UREM32Impl()
2831 B.buildSelect(DstReg, Cond, B.buildAdd(S32, Q, One), Q); in legalizeUDIV_UREM32Impl()
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| H A D | AMDGPURegisterBankInfo.cpp | 136 B.buildSelect(DstReg, SrcReg, True, False); in applyBank()
1958 auto S = B.buildSelect(EltTy, Cmp, in foldExtractEltToCmpSelect()
2043 auto S = B.buildSelect(EltTy, Cmp, InsRegs[L], in foldInsertEltToCmpSelect()
2217 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2218 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
2498 B.buildSelect(DefRegs[0], SrcReg, True, False); in applyMappingImpl()
2501 auto Sel = B.buildSelect(SelType, SrcReg, True, False); in applyMappingImpl()
2505 B.buildSelect(DstReg, SrcReg, True, False); in applyMappingImpl()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 1100 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
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