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Searched refs:buildInstr (Results 1 – 25 of 28) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h375 MachineInstrBuilder buildInstr(unsigned Opcode) { in buildInstr() function
489 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); in buildPtrMask()
522 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); in buildUAddo()
528 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); in buildUSubo()
534 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1}); in buildSAddo()
540 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1}); in buildSSubo()
560 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
568 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
576 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
584 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
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H A DLegalizationArtifactCombiner.h77 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
177 Builder.buildInstr( in tryCombineSExt()
192 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineSExt()
335 Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {}); in tryFoldImplicitDef()
662 Builder.buildInstr(ConvertOp, {DstRegs[k]}, {TmpRegs[k]}); in tryCombineUnmergeValues()
705 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); in tryCombineUnmergeValues()
H A DCSEMIRBuilder.h94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp85 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
121 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
130 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); in buildDynStackAlloc()
140 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); in buildFrameIndex()
153 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); in buildGlobalValue()
161 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {}) in buildJumpTable()
189 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}); in buildPtrAdd()
219 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); in buildBr()
224 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
232 return buildInstr(TargetOpcode::G_BRJT) in buildBrJT()
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H A DCSEMIRBuilder.cpp167 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
209 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
213 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
230 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
H A DLegalizerHelper.cpp1045 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); in narrowScalar()
1174 .buildInstr( in narrowScalar()
1199 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, in narrowScalar()
1257 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); in widenScalarSrc()
1273 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); in widenScalarDst()
1282 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); in narrowScalarDst()
1586 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); in widenScalarUnmergeValues()
1761 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); in widenScalarAddSubOverflow()
1762 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); in widenScalarAddSubOverflow()
1768 .buildInstr(Opcode, {WideTy, CarryOutTy}, in widenScalarAddSubOverflow()
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H A DIRTranslator.cpp295 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
308 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
1455 MIRBuilder.buildInstr(Opcode, {Res}, {Op}); in translateCast()
1574 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1618 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); in getStackGuard()
1637 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1650 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
1766 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
1812 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags); in translateConstrainedFPIntrinsic()
1851 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI)); in translateKnownIntrinsic()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
412 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
716 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
738 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
867 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}) in getVectorFCMP()
868 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}); in getVectorFCMP()
874 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
875 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}) in getVectorFCMP()
881 ? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
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H A DAArch64InstructionSelector.cpp813 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg); in copySubReg()
1058 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1207 auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC); in emitSelect()
1391 MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); in emitTestBit()
1453 auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); in emitCBZ()
1470 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1472 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); in selectCompareBranchFedByFCmp()
1576 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB); in selectCompareBranchFedByICmp()
1610 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
1612 auto Bcc = MIB.buildInstr(AArch64::Bcc) in selectCompareBranch()
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H A DAArch64PostLegalizerCombiner.cpp105 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
216 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
266 B.buildInstr(TargetOpcode::G_SBFX, {Dst}, {ShiftSrc, Cst1, Cst2}); in matchBitfieldExtractFromSExtInReg()
H A DAArch64LegalizerInfo.cpp869 auto ADRP = MIRBuilder.buildInstr(AArch64::ADRP, {LLT::pointer(0, 64)}, {}) in legalizeSmallCMGlobalValue()
890 ADRP = MIRBuilder.buildInstr(AArch64::MOVKXi, {LLT::pointer(0, 64)}, {ADRP}) in legalizeSmallCMGlobalValue()
897 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP}) in legalizeSmallCMGlobalValue()
1111 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASDesired}, {}) in legalizeAtomicCmpxchg128()
1116 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {}) in legalizeAtomicCmpxchg128()
1122 CAS = MIRBuilder.buildInstr(Opcode, {CASDst}, {CASDesired, CASNew, Addr}); in legalizeAtomicCmpxchg128()
1131 CAS = MIRBuilder.buildInstr(AArch64::CMP_SWAP_128, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp413 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
435 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
912 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerTailCall()
1023 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0); in lowerTailCall()
1084 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerCall()
1157 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) in lowerCall()
H A DAArch64GlobalISelUtils.cpp90 .buildInstr(TargetOpcode::G_BZERO, {}, in tryEmitBZero()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp116 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); in applySelectFCmpToFMinToFMaxLegacy()
193 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, in applyUCharToFloat()
196 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, in applyUCharToFloat()
246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
H A DAMDGPURegisterBankInfo.cpp661 B.buildInstr(AMDGPU::G_UNMERGE_VALUES) in split64BitValueForMapping()
757 B.buildInstr(TargetOpcode::IMPLICIT_DEF) in executeInWaterfallLoop()
786 B.buildInstr(TargetOpcode::PHI) in executeInWaterfallLoop()
794 B.buildInstr(TargetOpcode::G_PHI) in executeInWaterfallLoop()
871 B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64) in executeInWaterfallLoop()
881 B.buildInstr(WaveAndOpc) in executeInWaterfallLoop()
965 B.buildInstr(CmpOp) in executeInWaterfallLoop()
974 B.buildInstr(WaveAndOpc) in executeInWaterfallLoop()
1003 B.buildInstr(AndSaveExecOpc) in executeInWaterfallLoop()
1010 B.buildInstr(XorTermOpc) in executeInWaterfallLoop()
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H A DAMDGPUPreLegalizerCombiner.cpp135 B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16}, in applyClampI64ToI16()
145 auto Med3 = B.buildInstr( in applyClampI64ToI16()
H A DAMDGPUCallLowering.cpp326 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
363 B.buildInstr(AMDGPU::S_ENDPGM) in lowerReturn()
1123 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); in lowerTailCall()
1217 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0); in lowerTailCall()
1295 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP) in lowerCall()
1377 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN) in lowerCall()
H A DAMDGPULegalizerInfo.cpp1757 B.buildInstr(AMDGPU::S_GETREG_B32) in getSegmentAperture()
2261 MachineInstrBuilder MIB = B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET) in buildPCRelGlobalAddress()
2508 B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG) in legalizeAtomicCmpXChg()
2807 auto RcpIFlag = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {FloatY}); in legalizeUDIV_UREM32Impl()
2860 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); in emitReciprocalU64()
3196 B.buildInstr(AMDGPU::S_DENORM_MODE) in toggleSPDenormMode()
3205 B.buildInstr(AMDGPU::S_SETREG_IMM32_B32) in toggleSPDenormMode()
3729 auto MIB = B.buildInstr(Opc) in legalizeBufferStore()
3832 auto MIB = B.buildInstr(Opc) in legalizeBufferLoad()
3873 B.buildInstr(Opc) in legalizeAtomicIncDec()
[all …]
H A DAMDGPURegBankCombiner.cpp137 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)}, in applyMed3()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
617 MachineInstrBuilder PairF64 = B.buildInstr( in select()
806 MachineInstrBuilder MIB = B.buildInstr( in select()
H A DMipsLegalizerInfo.cpp465 if (!MIRBuilder.buildInstr(Opcode) in SelectMSA3OpIntrinsic()
480 MIRBuilder.buildInstr(Opcode) in MSA3OpIntrinsicToGeneric()
492 MIRBuilder.buildInstr(Opcode) in MSA2OpIntrinsicToGeneric()
510 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); in legalizeIntrinsic()
H A DMipsCallLowering.cpp528 MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN); in lowerCall()
632 MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0); in lowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp35 MIRBuilder.buildInstr(PPC::BLR8); in lowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallLowering.cpp303 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
345 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
391 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp466 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN); in lowerCall()
533 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP) in lowerCall()

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