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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td32 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
41 let AsmString = asmstr;
47 dag outs, dag ins, string asmstr, list<dag> pattern>
48 : MSP430Inst<outs, ins, size, asmstr> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
68 dag outs, dag ins, string asmstr, list<dag> pattern>
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
74 dag outs, dag ins, string asmstr, list<dag> pattern>
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td12 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
19 let AsmString = asmstr;
26 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27 : InstXCore<0, outs, ins, asmstr, pattern> {
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstXCore<2, outs, ins, asmstr, pattern> {
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
25 let AsmString = asmstr;
77 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
91 let AsmString = asmstr;
112 class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
114 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
117 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
119 : I<opcode, OOL, IOL, asmstr, itin> {
129 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
130 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
[all …]
H A DPPCInstrPrefix.td66 class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
76 let AsmString = asmstr;
107 class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
109 : I<4, OOL, IOL, asmstr, itin> {
126 string asmbase, string asmstr,
130 !strconcat(asmbase, !strconcat(" ", asmstr)),
134 !strconcat(asmbase, !strconcat(". ", asmstr)),
139 class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
141 : PI<1, opcode, OOL, IOL, asmstr, itin> {
160 class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
[all …]
H A DPPCInstrSPE.td14 class EFXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
16 I<4, OOL, IOL, asmstr, itin> {
29 class EFXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
31 EFXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
35 class EFXForm_2a<bits<11> xo, dag OOL, dag IOL, string asmstr,
37 EFXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
41 class EFXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
43 I<4, OOL, IOL, asmstr, itin> {
55 class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
57 I<4, OOL, IOL, asmstr, itin> {
[all …]
H A DPPCInstrInfo.td1188 string asmbase, string asmstr, InstrItinClass itin,
1192 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1196 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1202 string asmbase, string asmstr, InstrItinClass itin,
1207 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1211 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1217 string asmbase, string asmstr, InstrItinClass itin,
1222 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1226 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1232 string asmbase, string asmstr, InstrItinClass itin,
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrFormats.td96 class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
102 let AsmString = asmstr;
120 class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
121 : InstARC<0, outs, ins, asmstr, pattern> {
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
157 InstARC<4, outs, ins, asmstr, pattern> {
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
167 F32_BR<major, outs, ins, b16, asmstr, pattern> {
175 class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
177 F32_BR<major, outs, ins, b16, asmstr, pattern> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td14 class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction
20 let AsmString = asmstr;
27 class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : AVRInst<outs, ins, asmstr, pattern>
36 class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
37 : AVRInst<outs, ins, asmstr, pattern>
52 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
53 : AVRInst16<outs, ins, asmstr, pattern>
69 class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
70 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td9 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
22 let AsmString = asmstr;
36 class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
38 : InstSP<outs, ins, asmstr, pattern, itin> {
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
50 : F2<outs, ins, asmstr, pattern, itin> {
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
60 : F2<outs, ins, asmstr, pattern, itin> {
69 dag outs, dag ins, string asmstr, list<dag> pattern,
71 : InstSP<outs, ins, asmstr, pattern, itin> {
[all …]
H A DSparcInstrVIS.td14 class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
16 : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
31 class VISInst0<bits<9> opfval, string asmstr>
32 : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
H A DSparcInstrInfo.td434 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
435 : InstSP<outs, ins, asmstr, pattern> {
792 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
793 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
807 class BranchSP<dag ins, string asmstr, list<dag> pattern>
808 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
811 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
812 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
866 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
867 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td35 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
44 let AsmString = asmstr;
54 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
56 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
71 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
73 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
81 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
83 MipsInst16_32<outs, ins, asmstr, pattern, itin>
91 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
92 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
[all …]
H A DMips16InstrInfo.td53 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
55 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
62 class FI816_ins_base<bits<3> _func, string asmstr,
64 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
67 class FI816_ins<bits<3> _func, string asmstr,
69 FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>;
71 class FI816_SP_ins<bits<3> _func, string asmstr,
73 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
80 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
83 !strconcat(asmstr, asmstr2), [], itin>;
[all …]
H A DMipsInstrFormats.td71 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
89 let AsmString = asmstr;
115 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
117 MipsInst<outs, ins, asmstr, pattern, itin, f> {
141 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
142 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
153 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrFormats.td23 class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
35 let AsmString = asmstr;
68 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
69 : InstVE<outs, ins, asmstr, pattern> {
94 class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
96 : RM<opVal, outs, ins, asmstr, pattern>;
100 class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
102 : RRM<opVal, outs, ins, asmstr, pattern> {
115 class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
116 : InstVE<outs, ins, asmstr, pattern> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td17 class WebAssemblyInst<bits<32> inst, string asmstr, string stack, string is64>
26 let AsmString = asmstr;
34 string asmstr = "", bits<32> inst = -1, string is64 = "false">
35 : WebAssemblyInst<inst, asmstr, stack, is64> {
44 // based version of this instruction, as well as the corresponding asmstr.
65 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
67 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrFormats.td9 class InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern>
23 let AsmString = asmstr;
86 class InstRI<bits<3> op, dag outs, dag ins, string asmstr,
88 : InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> {
146 class InstRR<bits<3> op, dag outs, dag ins, string asmstr,
148 : InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> {
196 class InstRM<bit S, dag outs, dag ins, string asmstr, list<dag> pattern>
197 : InstLanai<outs, ins, asmstr, pattern> {
256 class InstRRM<bit S, dag outs, dag ins, string asmstr,
258 : InstLanai<outs, ins, asmstr, pattern> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td50 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
57 let AsmString = asmstr;
194 class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
195 InstHexagon<outs, ins, asmstr, [], "", itin, type>;
202 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
204 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
206 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
208 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
211 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
213 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
[all …]
H A DHexagonInstrFormatsV65.td23 class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr,
26 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>;
28 class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr,
31 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_GATHER>;
H A DHexagonInstrFormatsV60.td17 class CVI_VA_Resource<dag outs, dag ins, string asmstr,
20 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td13 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
21 let AsmString = asmstr;
189 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
190 : InstSystemZ<2, outs, ins, asmstr, pattern> {
197 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
198 : InstSystemZ<2, outs, ins, asmstr, pattern> {
208 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
209 : InstSystemZ<4, outs, ins, asmstr, pattern> {
222 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
223 : InstSystemZ<6, outs, ins, asmstr, pattern> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrFormats.td100 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
114 let AsmString = asmstr;
119 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
120 : InstBPF<outs, ins, asmstr, pattern> {
H A DBPFInstrInfo.td134 dag outs, dag ins, string asmstr, list<dag> pattern>
135 : InstBPF<outs, ins, asmstr, pattern> {
149 dag outs, dag ins, string asmstr, list<dag> pattern>
150 : InstBPF<outs, ins, asmstr, pattern> {
244 dag outs, dag ins, string asmstr, list<dag> pattern>
245 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, outs, ins, asmstr, pattern> {
255 dag outs, dag ins, string asmstr, list<dag> pattern>
256 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, outs, ins, asmstr, pattern> {
304 dag outs, dag ins, string asmstr, list<dag> pattern>
305 : TYPE_ALU_JMP<Opc.Value, 0, outs, ins, asmstr, pattern> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td22 class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
29 let AsmString = asmstr;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td22 class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
30 let AsmString = asmstr;
36 class CSKYPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
37 : CSKYInst<AddrModeNone, 0, outs, ins, asmstr, pattern> {
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
44 : CSKYInst<am, 4, outs, ins, asmstr, pattern> {

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