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Searched refs:addUse (Results 1 – 25 of 37) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp279 .addUse(TiedDest) in buildUnalignedLoad()
334 .addUse(PseudoMULTuReg); in select()
363 .addUse(Mips::ZERO) in select()
376 .addUse(I.getOperand(2).getReg()) in select()
384 .addUse(I.getOperand(0).getReg()) in select()
385 .addUse(JTIndex); in select()
393 .addUse(DestAddress) in select()
405 .addUse(DestTmp) in select()
406 .addUse(MF.getInfo<MipsFunctionInfo>() in select()
414 .addUse(Dest); in select()
[all …]
H A DMipsISelLowering.cpp4752 .addUse(Address) in emitLDR_W()
4754 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4764 .addUse(Address) in emitLDR_W()
4766 .addUse(Undef); in emitLDR_W()
4769 .addUse(Address) in emitLDR_W()
4771 .addUse(LoadHalf); in emitLDR_W()
4772 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4799 .addUse(Address) in emitLDR_D()
4801 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4808 .addUse(Address) in emitLDR_D()
[all …]
H A DMipsSEISelDAGToDAG.cpp135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
H A DMipsCallLowering.cpp255 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
543 MIB.addUse(CalleeReg); in lowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
[all …]
H A DAArch64ExpandPseudoInsts.cpp305 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
306 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
313 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
314 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
317 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
611 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB); in expandSetTagLoop()
711 .addUse(CtxReg) in expandStoreSwiftAsyncContext()
712 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
728 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
733 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp313 .addUse(AArch64::SP) in getOrCreateFrameHelper()
329 .addUse(AArch64::LR) in getOrCreateFrameHelper()
557 .addUse(AArch64::SP) in lowerProlog()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1967 .addUse(Hi) in extractF64Exponent()
1968 .addUse(Const0.getReg(0)) in extractF64Exponent()
1969 .addUse(Const1.getReg(0)); in extractF64Exponent()
2041 .addUse(CvtHi.getReg(0)) in legalizeITOFP()
2042 .addUse(ThirtyTwo.getReg(0)); in legalizeITOFP()
2203 .addUse(MulVal.getReg(0)) in legalizeSinCos()
2211 .addUse(TrigVal) in legalizeSinCos()
2510 .addUse(PtrReg) in legalizeAtomicCmpXChg()
2511 .addUse(PackedVal) in legalizeAtomicCmpXChg()
2560 .addUse(Log.getReg(0)) in legalizeFPow()
[all …]
H A DAMDGPURegisterBankInfo.cpp664 .addUse(Reg); in split64BitValueForMapping()
1494 .addUse(RSrc) // rsrc in applyMappingSBufferLoad()
1495 .addUse(VIndex) // vindex in applyMappingSBufferLoad()
1496 .addUse(VOffset) // voffset in applyMappingSBufferLoad()
1497 .addUse(SOffset) // soffset in applyMappingSBufferLoad()
1797 .addUse(VData); in selectStoreIntrinsic()
1800 MIB.addUse(VOffset); in selectStoreIntrinsic()
1802 MIB.addUse(RSrc) in selectStoreIntrinsic()
1803 .addUse(SOffset) in selectStoreIntrinsic()
1826 .addUse(SrcReg); in buildVCopy()
[all …]
H A DSIFormMemoryClauses.cpp392 Kill.addUse(Reg, std::get<0>(Op), std::get<1>(Op)); in runOnMachineFunction()
H A DAMDGPUCallLowering.cpp79 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
212 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
377 Ret.addUse(ReturnAddrVReg); in lowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp581 .addUse(LHSReg) in insertComparison()
582 .addUse(RHSReg) in insertComparison()
600 .addUse(PrevRes) in insertComparison()
778 .addUse(CondReg) in selectSelect()
794 .addUse(TrueReg) in selectSelect()
795 .addUse(FalseReg) in selectSelect()
888 .addUse(AndResult) in select()
938 .addUse(SrcReg) in select()
1109 .addUse(OriginalValue) in select()
H A DARMCallLowering.cpp121 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp939 .addUse(SrcReg) in selectCopy()
1702 Shl.addUse(Src2Reg); in selectVectorSHL()
1789 .addUse(ArgsAddrReg) in selectVaStartDarwin()
1790 .addUse(ListReg) in selectVaStartDarwin()
1817 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2483 .addUse(SrcReg, 0, Offset == 0 ? AArch64::sube64 : AArch64::subo64); in select()
2546 .addUse(I.getOperand(2).getReg()) in select()
2653 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()
2698 .addUse(LdReg) in select()
2926 .addUse(SrcReg) in select()
[all …]
H A DAArch64LegalizerInfo.cpp1059 .addUse(CTPOP.getReg(0)); in legalizeCTPOP()
1112 .addUse(DesiredI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
1114 .addUse(DesiredI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
1117 .addUse(NewI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
1119 .addUse(NewI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp274 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
457 MIB.addUse(AArch64::X21, RegState::Implicit); in lowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp224 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
233 .addUse(TablePtr) in buildBrJT()
235 .addUse(IndexReg); in buildBrJT()
806 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
807 .addUse(CmpVal) in buildAtomicCmpXchgWithSuccess()
808 .addUse(NewVal) in buildAtomicCmpXchgWithSuccess()
831 .addUse(Addr) in buildAtomicCmpXchg()
832 .addUse(CmpVal) in buildAtomicCmpXchg()
833 .addUse(NewVal) in buildAtomicCmpXchg()
H A DRegBankSelect.cpp166 .addUse(Src); in repairReg()
198 MergeBuilder.addUse(SrcReg); in repairReg()
207 UnMergeBuilder.addUse(MO.getReg()); in repairReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp763 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
764 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
768 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
769 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallLowering.cpp109 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
348 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
H A DX86FrameLowering.cpp1368 .addUse(MachineFramePtr) in emitPrologue()
1514 .addUse(X86::RSP) in emitPrologue()
1516 .addUse(X86::NoRegister) in emitPrologue()
1518 .addUse(X86::NoRegister) in emitPrologue()
1521 .addUse(X86::RSP) in emitPrologue()
2044 .addUse(MachineFramePtr) in emitEpilogue()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DValue.h514 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
875 if (V) V->addUse(*this); in set()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1044 void addUse(SDUse &U) { U.addToList(&UseList); }
1186 if (V.getNode()) V.getNode()->addUse(*this);
1191 V.getNode()->addUse(*this);
1197 if (N) N->addUse(*this);
H A DMachineInstrBuilder.h123 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h147 MIB.addUse(Reg); in addSrcToMIB()
150 MIB.addUse(SrcMIB->getOperand(0).getReg()); in addSrcToMIB()

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