| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
124 .addImm(0); in lowerSubvectorStore()
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| H A D | SystemZInstrInfo.cpp | 229 .addImm(32); in expandLoadStackGuard()
237 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0); in expandLoadStackGuard()
269 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate); in emitGRX32Move()
505 .addImm(CCValid).addImm(CCMask).addMBB(TBB); in insertBranch()
606 .addImm(CCValid).addImm(CCMask); in insertSelect()
729 .addImm(CCValid).addImm(CCMask) in PredicateInstruction()
736 .addImm(CCValid).addImm(CCMask) in PredicateInstruction()
747 .addImm(CCValid) in PredicateInstruction()
748 .addImm(CCMask) in PredicateInstruction()
761 .addImm(CCValid).addImm(CCMask) in PredicateInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 154 .addImm(0) in emitPrologueInsns()
155 .addImm(0) in emitPrologueInsns()
159 .addImm(0) in emitPrologueInsns()
160 .addImm(8) in emitPrologueInsns()
166 .addImm(0) in emitPrologueInsns()
167 .addImm(24) in emitPrologueInsns()
171 .addImm(0) in emitPrologueInsns()
172 .addImm(32) in emitPrologueInsns()
178 .addImm(0) in emitPrologueInsns()
179 .addImm(40) in emitPrologueInsns()
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| H A D | VEInstrInfo.cpp | 342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
367 .addImm(0); in copyPhysReg()
379 .addImm(0) in copyPhysReg()
380 .addImm(0) in copyPhysReg()
381 .addImm(256); in copyPhysReg()
383 .addImm(M1(0)) // Represent (0)1. in copyPhysReg()
474 .addImm(0) in storeRegToStackSlot()
475 .addImm(0) in storeRegToStackSlot()
481 .addImm(0) in storeRegToStackSlot()
482 .addImm(0) in storeRegToStackSlot()
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| H A D | VEISelLowering.cpp | 1818 .addImm(0) in prepareMBB()
1819 .addImm(0) in prepareMBB()
1823 .addImm(M0(32)); in prepareMBB()
1834 .addImm(0) in prepareMBB()
1835 .addImm(0) in prepareMBB()
1839 .addImm(M0(32)); in prepareMBB()
1842 .addImm(0) in prepareMBB()
1879 .addImm(0) in prepareSymbol()
1880 .addImm(0) in prepareSymbol()
1884 .addImm(M0(32)); in prepareSymbol()
[all …]
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| H A D | VEInstrBuilder.h | 35 return MIB.addFrameIndex(FI).addImm(0).addImm(Offset);
36 return MIB.addFrameIndex(FI).addImm(Offset);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 148 .addImm(ConstVal->Value.getBoolValue() ? -1 : 0); in selectCOPY()
159 .addImm(1) in selectCOPY()
162 .addImm(0) in selectCOPY()
341 .addImm(0); in selectG_ADD_SUB()
375 .addImm(0); in selectG_ADD_SUB()
381 .addImm(0); in selectG_ADD_SUB()
389 .addImm(AMDGPU::sub0) in selectG_ADD_SUB()
391 .addImm(AMDGPU::sub1); in selectG_ADD_SUB()
527 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
623 .addImm(Lo16 | (Hi16 << 16)); in selectG_BUILD_VECTOR_TRUNC()
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| H A D | R600ControlFlowFinalizer.cpp | 323 .addImm(0) // ADDR in MakeFetchClause()
324 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
372 .addImm(LiteralPair0) in insertLiterals()
373 .addImm(LiteralPair1); in insertLiterals()
415 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
422 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
428 MILit.addImm(0); in MakeALUClause()
442 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount); in EmitFetchClause()
454 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount); in EmitALUClause()
524 .addImm(CfCount + 1) in runOnMachineFunction()
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| H A D | R600EmitClauseMarkers.cpp | 281 .addImm(Address++) // ADDR in MakeALUClause()
282 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0 in MakeALUClause()
283 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1 in MakeALUClause()
284 .addImm(KCacheBanks.empty()?0:2) // KM0 in MakeALUClause()
285 .addImm((KCacheBanks.size() < 2)?0:2) // KM1 in MakeALUClause()
286 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0 in MakeALUClause()
287 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1 in MakeALUClause()
288 .addImm(AluInstCount) // COUNT in MakeALUClause()
289 .addImm(1); // Enabled in MakeALUClause()
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| H A D | SIFrameLowering.cpp | 171 .addImm(MFI->getGITPtrHigh()) in buildGitPtr()
249 .addImm(EncodedOffset) // offset in emitEntryFunctionFlatScratchInit()
250 .addImm(0) // cpol in emitEntryFunctionFlatScratchInit()
257 .addImm(0xffff); in emitEntryFunctionFlatScratchInit()
279 .addImm(0); in emitEntryFunctionFlatScratchInit()
282 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_LO | in emitEntryFunctionFlatScratchInit()
286 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_HI | in emitEntryFunctionFlatScratchInit()
297 .addImm(0); in emitEntryFunctionFlatScratchInit()
317 .addImm(8); in emitEntryFunctionFlatScratchInit()
487 .addImm(MF.getFrameInfo().getStackSize() * getScratchScaleFactor(ST)); in emitEntryFunctionPrologue()
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| H A D | SIInstrInfo.cpp | 690 .addImm(1) in copyPhysReg()
691 .addImm(0); in copyPhysReg()
703 .addImm(0) in copyPhysReg()
723 .addImm(1) in copyPhysReg()
724 .addImm(0); in copyPhysReg()
736 .addImm(0) in copyPhysReg()
763 .addImm(0); in copyPhysReg()
768 .addImm(0); in copyPhysReg()
847 .addImm(0) // src0_modifiers in copyPhysReg()
849 .addImm(0) // clamp in copyPhysReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 187 .addImm(ARMCC::AL) in runOnMachineFunction()
1024 .addImm(ARMCC::AL) in emitJumpTableInsts()
1333 .addImm(MI->getOperand(2).getImm()) in emitInstruction()
1349 .addImm(MI->getOperand(2).getImm()) in emitInstruction()
1360 .addImm(ARMCC::AL) in emitInstruction()
1397 .addImm(ARMCC::AL).addReg(0) in emitInstruction()
1406 .addImm(ARMCC::AL) in emitInstruction()
1415 .addImm(ARMCC::AL) in emitInstruction()
1426 .addImm(ARMCC::AL) in emitInstruction()
1439 .addImm(ARMCC::AL) in emitInstruction()
[all …]
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| H A D | MVETailPredUtils.h | 95 MIB.addImm(0);
96 MIB.addImm(ARMCC::AL);
103 MIB.addImm(0);
104 MIB.addImm(ARMCC::AL);
113 MIB.addImm(ARMCC::EQ); // condition code
138 MIB.addImm(ARMCC::AL);
160 MIB.addImm(0);
161 MIB.addImm(ARMCC::AL);
169 MIB.addImm(ARMCC::NE); // condition code
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
187 MIB.addImm(AM.Disp); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
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| H A D | X86FrameLowering.cpp | 227 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); in emitSPUpdate()
245 .addImm(Offset) in emitSPUpdate()
271 .addImm(Offset) in emitSPUpdate()
357 .addImm(AbsOffset); in BuildStackAdjustment()
495 .addImm(0 /* no explicit stack size */); in emitStackProbe()
579 .addImm(StackProbeSize - AlignOffset) in emitStackProbeInlineGenericBlock()
591 .addImm(0) in emitStackProbeInlineGenericBlock()
603 .addImm(StackProbeSize) in emitStackProbeInlineGenericBlock()
615 .addImm(0) in emitStackProbeInlineGenericBlock()
625 .addImm(ChunkSize) in emitStackProbeInlineGenericBlock()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 80 .addImm(I * Alignment); in expandMEMCPY()
83 .addImm(I * Alignment); in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
137 .addImm(0); in storeRegToStackSlot()
142 .addImm(0); in storeRegToStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 307 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); in EmitSled()
310 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in EmitSled()
390 .addImm(4) in EmitHwasanMemaccessSymbols()
391 .addImm(55), in EmitHwasanMemaccessSymbols()
398 .addImm(0) in EmitHwasanMemaccessSymbols()
399 .addImm(0), in EmitHwasanMemaccessSymbols()
406 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), in EmitHwasanMemaccessSymbols()
411 .addImm(AArch64CC::NE) in EmitHwasanMemaccessSymbols()
425 .addImm(56) in EmitHwasanMemaccessSymbols()
426 .addImm(63), in EmitHwasanMemaccessSymbols()
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| H A D | AArch64SpeculationHardening.cpp | 221 BuildMI(MBB, MBBI, DL, TII->get(AArch64::DSB)).addImm(0xf); in insertFullSpeculationBarrier()
222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf); in insertFullSpeculationBarrier()
235 .addImm(CondCode); in insertTrackingCode()
372 .addImm(0) in insertSPToRegTaintPropagation()
373 .addImm(0); // no shift in insertSPToRegTaintPropagation()
379 .addImm(AArch64CC::EQ); in insertSPToRegTaintPropagation()
395 .addImm(0) in insertRegToSPTaintPropagation()
396 .addImm(0); // no shift in insertRegToSPTaintPropagation()
402 .addImm(0); in insertRegToSPTaintPropagation()
407 .addImm(0) in insertRegToSPTaintPropagation()
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| H A D | AArch64ExpandPseudoInsts.cpp | 150 .addImm(I->Op2)); in expandMOVImm()
161 .addImm(I->Op1) in expandMOVImm()
162 .addImm(I->Op2)); in expandMOVImm()
174 .addImm(I->Op1) in expandMOVImm()
175 .addImm(I->Op2)); in expandMOVImm()
216 .addImm(0).addImm(0); in expandCMP_SWAP()
222 .addImm(ExtendImm); in expandCMP_SWAP()
224 .addImm(AArch64CC::NE) in expandCMP_SWAP()
303 .addImm(0); in expandCMP_SWAP_128()
307 .addImm(AArch64CC::EQ); in expandCMP_SWAP_128()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiFrameLowering.cpp | 80 .addImm(MaxCallFrameSize); in replaceAdjDynAllocPseudo()
116 .addImm(-4) in emitPrologue()
117 .addImm(LPAC::makePreOp(LPAC::ADD)) in emitPrologue()
124 .addImm(8) in emitPrologue()
132 .addImm(StackSize) in emitPrologue()
188 .addImm(0); in emitEpilogue()
193 .addImm(-8) in emitEpilogue()
194 .addImm(LPAC::ADD); in emitEpilogue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 812 .addImm(CRSaveOffset) in emitPrologue()
826 .addImm(FPOffset) in emitPrologue()
831 .addImm(PBPOffset) in emitPrologue()
836 .addImm(BPOffset) in emitPrologue()
846 .addImm(LROffset) in emitPrologue()
864 .addImm(ImmOffset) in emitPrologue()
874 .addImm(CRSaveOffset) in emitPrologue()
907 .addImm(NegFrameSize); in emitPrologue()
923 .addImm(0) in emitPrologue()
924 .addImm(64 - Log2(MaxAlign)); in emitPrologue()
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| H A D | PPCBranchSelector.cpp | 374 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); in runOnMachineFunction()
377 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
380 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
382 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
384 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
386 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
388 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); in runOnMachineFunction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in insertBranch()
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in insertBranch()
410 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
413 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
416 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
419 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
422 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
427 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
448 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
451 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 650 .addImm(Off); in splitMemRef()
653 .addImm(Off+4); in splitMemRef()
659 .addImm(Off) in splitMemRef()
663 .addImm(Off+4) in splitMemRef()
677 .addImm(Inc); in splitMemRef()
719 .addImm(int32_t(V & 0xFFFFFFFFULL)); in splitImmediate()
721 .addImm(int32_t(V >> 32)); in splitImmediate()
771 .addImm(31); in splitExt()
840 .addImm(S); in splitShift()
846 .addImm(S) in splitShift()
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| H A D | HexagonCopyToCombine.cpp | 666 .addImm(V); in emitConst64()
681 .addImm(LoOperand.getImm()); in emitCombineII()
686 .addImm(HiOperand.getImm()) in emitCombineII()
697 .addImm(LoOperand.getImm()); in emitCombineII()
702 .addImm(HiOperand.getImm()) in emitCombineII()
712 .addImm(LoOperand.getImm()); in emitCombineII()
717 .addImm(HiOperand.getImm()) in emitCombineII()
727 .addImm(LoOperand.getImm()); in emitCombineII()
732 .addImm(HiOperand.getImm()) in emitCombineII()
743 .addImm(HiOperand.getImm()) in emitCombineII()
[all …]
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