| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 398 bool RegisterFile::tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes, in tryEliminateMoveOrSwap() argument
400 if (Writes.size() != Reads.size()) in tryEliminateMoveOrSwap()
407 if (Writes.empty() || Writes.size() > 2) in tryEliminateMoveOrSwap()
412 RegisterMappings[Writes[0].getRegisterID()].second; in tryEliminateMoveOrSwap()
418 (RMT.NumMoveEliminated + Writes.size()) > RMT.MaxMoveEliminatedPerCycle) in tryEliminateMoveOrSwap()
421 for (size_t I = 0, E = Writes.size(); I < E; ++I) { in tryEliminateMoveOrSwap()
423 const WriteState &WS = Writes[E - (I + 1)]; in tryEliminateMoveOrSwap()
428 for (size_t I = 0, E = Writes.size(); I < E; ++I) { in tryEliminateMoveOrSwap()
430 WriteState &WS = Writes[E - (I + 1)]; in tryEliminateMoveOrSwap()
476 SmallVectorImpl<WriteRef> &Writes, in collectWrites() argument
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleA57.td | 67 list <SchedWriteRes> Writes = writes;
531 SchedVar<A57LMAddrPred1, A57LDMOpsListNoregin.Writes[0-1]>,
532 SchedVar<A57LMAddrPred2, A57LDMOpsListNoregin.Writes[0-3]>,
533 SchedVar<A57LMAddrPred3, A57LDMOpsListNoregin.Writes[0-5]>,
534 SchedVar<A57LMAddrPred4, A57LDMOpsListNoregin.Writes[0-7]>,
535 SchedVar<A57LMAddrPred5, A57LDMOpsListNoregin.Writes[0-9]>,
536 SchedVar<A57LMAddrPred6, A57LDMOpsListNoregin.Writes[0-11]>,
537 SchedVar<A57LMAddrPred7, A57LDMOpsListNoregin.Writes[0-13]>,
538 SchedVar<A57LMAddrPred8, A57LDMOpsListNoregin.Writes[0-15]>,
539 SchedVar<NoSchedPred, A57LDMOpsListNoregin.Writes[0-15]>
[all …]
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| H A D | ARMScheduleA9.td | 1882 list <WriteSequence> Writes = writes;
2110 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2111 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2112 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2113 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2114 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2115 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2116 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2117 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2215 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
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| H A D | ARMParallelDSP.cpp | 352 SmallVector<Instruction*, 8> Writes; in RecordMemoryOps() local
361 Writes.push_back(&I); in RecordMemoryOps()
378 for (auto Write : Writes) { in RecordMemoryOps()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 756 IdxVec &Writes, IdxVec &Reads) const { in findRWs() argument
760 findRWs(WriteDefs, Writes, false); in findRWs()
874 IdxVec Writes, Reads; in collectSchedClasses() local
876 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
879 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0}); in collectSchedClasses()
920 if (!SC.Writes.empty()) { in collectSchedClasses()
924 for (unsigned int Write : SC.Writes) in collectSchedClasses()
938 IdxVec Writes; in collectSchedClasses() local
941 Writes, Reads); in collectSchedClasses()
943 for (unsigned WIdx : Writes) in collectSchedClasses()
[all …]
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| H A D | CodeGenSchedule.h | 132 IdxVec Writes; member
152 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
562 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
638 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| H A D | SubtargetEmitter.cpp | 1023 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
1037 Writes.clear(); in GenSchedClassTables()
1040 Writes, Reads); in GenSchedClassTables()
1043 if (Writes.empty()) { in GenSchedClassTables()
1049 Writes, Reads); in GenSchedClassTables()
1053 if (Writes.empty()) { in GenSchedClassTables()
1065 for (unsigned W : Writes) { in GenSchedClassTables()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 307 ID.Writes.resize(TotalDefs + NumVariadicOps); in populateWrites()
324 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
351 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
378 WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; in populateWrites()
410 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
424 ID.Writes.resize(CurrentDef); in populateWrites()
680 if (D.Writes.empty()) in createInstruction()
685 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
694 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCInstrAnalysis.cpp | 21 APInt &Writes) const { in clearsSuperRegisters()
22 Writes.clearAllBits(); in clearsSuperRegisters()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | LoopDataPrefetch.cpp | 235 bool Writes; member
241 : LSCEVAddRec(L), InsertPt(nullptr), Writes(false), MemI(nullptr) { in Prefetch()
254 Writes = isa<StoreInst>(I); in addInstruction()
265 Writes = true; in addInstruction()
404 ConstantInt::get(I32, P.Writes), in runOnLoop()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CalcSpillWeights.cpp | 253 bool Reads, Writes; in weightCalcHelper() local
254 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in weightCalcHelper()
255 Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI); in weightCalcHelper()
258 if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB)) in weightCalcHelper()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| H A D | InOrderIssueStage.cpp | 97 SmallVector<WriteRef, 4> Writes; in checkRegisterHazard() local
104 PRF.collectWrites(STI, RS, Writes, CommittedWrites); in checkRegisterHazard()
105 for (const WriteRef &WR : Writes) { in checkRegisterHazard()
125 Writes.clear(); in checkRegisterHazard()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 277 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
278 DependentWrites = Writes; in setDependentWrites()
279 IsReady = !Writes; in setDependentWrites()
349 SmallVector<WriteDescriptor, 4> Writes; // Implicit writes are at the end. member
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | RegisterFile.h | 237 SmallVectorImpl<WriteRef> &Writes,
267 bool tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
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| /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| H A D | seqstat.s | 16 # Writes to SEQSTAT should be ignored
|
| /netbsd-src/sys/arch/x68k/stand/libdos/ |
| H A D | dos_cerror.S | 1 | Writes Human68k DOS error number to dos_errno.
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| H A D | dos_procerr.S | 1 | Writes Human68k DOS process error number to dos_errno.
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | IntrinsicsARM.td | 96 // Writes to the GE bits.
103 // Writes to the GE bits.
106 // Writes to the GE bits.
117 // Writes to the GE bits.
137 // Writes to the GE bits.
140 // Writes to the GE bits.
151 // Writes to the GE bits.
154 // Writes to the GE bits.
157 // Writes to the GE bits.
160 // Writes to the GE bits.
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/gn/build/ |
| H A D | write_vcsrevision.gni | 8 # Writes "$foo_REVISION" and "$foo_REPOSITORY" for each foo in names.
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrAnalysis.h | 88 APInt &Writes) const;
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| /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/aarch64/ |
| H A D | testutils.inc | 19 # Writes the string in X1 to stdout
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 224 bool Writes; member
|
| /netbsd-src/distrib/amiga/stand/ |
| H A D | device-streams.README.md | 61 * streamtodev: Writes data from a stream into a device.
|
| /netbsd-src/crypto/external/bsd/openssl.old/dist/doc/man1/ |
| H A D | rand.pod | 54 Writes random data to the specified I<file> upon exit.
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| /netbsd-src/sys/external/isc/atheros_hal/dist/ar5416/ |
| H A D | ar9160.ini | 19 /* Auto Generated PCI Register Writes. Created: 05/22/08 */
629 /* Auto generated PCI Register Writes for SOWL1.0 ADDAC Shift Chain */
665 /* Auto generated PCI Register Writes for SOWL1.1 ADDAC Shift Chain */
|