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Searched refs:WriteSequence (Results 1 – 15 of 15) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td404 def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
405 def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
406 def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
407 def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
408 def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
409 def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
410 def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
411 def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
412 def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
413 def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td54 def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
58 def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;
65 def WriteSTX : WriteSequence<[WriteST, WriteLD]>;
89 def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>;
90 def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>;
93 def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>;
94 def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>;
H A DAArch64SchedCyclone.td356 def CyWriteCopyToFPR : WriteSequence<[WriteVLD, WriteV]>;
360 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
580 def CyWriteCvtToFPR : WriteSequence<[WriteVLD, CyWriteV4]>;
584 def CyWriteCvtToGPR : WriteSequence<[CyWriteV6, WriteLD]>;
H A DAArch64SchedExynosM3.td420 def M3WriteVSTA : WriteSequence<[WriteVST], 2>;
421 def M3WriteVSTB : WriteSequence<[WriteVST], 3>;
422 def M3WriteVSTC : WriteSequence<[WriteVST], 4>;
H A DAArch64SchedExynosM4.td424 def M4WriteVSTA : WriteSequence<[WriteVST], 2>;
425 def M4WriteVSTB : WriteSequence<[WriteVST], 3>;
426 def M4WriteVSTC : WriteSequence<[WriteVST], 4>;
H A DAArch64SchedFalkorDetails.td1237 def : InstRW<[WriteSequence<[FalkorWr_1XYZ_1cyc, FalkorWr_1XYZ_1cyc]>],
1239 def : InstRW<[WriteSequence<[FalkorWr_1LD_3cyc, FalkorWr_1XYZ_1cyc]>],
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td80 def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>;
81 def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>;
105 def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>;
107 def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle,
173 def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
513 def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>;
586 def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>;
631 def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
634 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
637 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
[all …]
H A DARMScheduleA9.td1881 class A9WriteLMOpsListType<list<WriteSequence> writes> {
1882 list <WriteSequence> Writes = writes;
2039 def A9WriteCycle#NumCycles : WriteSequence<[A9WriteCycle1], NumCycles>;
2047 def A9WriteAdr#NumAddr : WriteSequence<[A9WriteAdr], NumAddr>;
2085 def A9WriteL#NumAddr : WriteSequence<
2087 def A9WriteL#NumAddr#Hi : WriteSequence<
2108 // they may need to be part of a WriteSequence that includes A9WriteIssue.
2145 def A9WriteLfp#NumAddr#Seq : WriteSequence<[A9WriteLfpOp], NumAddr>;
2150 def A9WriteLfp#NumAddr : WriteSequence<
2155 def A9WriteLfp#NumAddr#Mov : WriteSequence<
[all …]
H A DARMScheduleA57.td249 WriteSequence<[A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_1cyc_1I]>;
251 WriteSequence<[A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_4cyc_1L]>;
H A DARMScheduleR52.td457 def R52WriteISTM#NumAddr : WriteSequence<[R52WriteIStIncAddr], NumAddr>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td533 // FIXME: This isn't quite right since the implementation of WriteSequence
536 def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits,
539 // FIXME: This isn't quite right since the implementation of WriteSequence
542 def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
545 // FIXME: This isn't quite right since the implementation of WriteSequence
548 def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
551 // FIXME: This isn't quite right since the implementation of WriteSequence
554 def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits,
557 // FIXME: This isn't quite right since the implementation of WriteSequence
560 def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td29 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86Schedule.td128 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
133 def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
134 def WriteADCRMW : WriteSequence<[WriteADCLd, WriteRMW]>;
184 def WriteBitTestSetImmRMW : WriteSequence<[WriteBitTestSetImmLd, WriteRMW]>;
185 def WriteBitTestSetRegRMW : WriteSequence<[WriteBitTestSetRegLd, WriteRMW]>;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSchedule.td241 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
298 // by defining a WriteSequence, or simply listing extra writes in the
449 // SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp1620 for (const auto &WriteSequence : Trans.WriteSequences) { in substituteVariants() local
1627 substituteVariantOperand(WriteSequence, /*IsRead=*/false, StartIdx); in substituteVariants()