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Searched refs:WREG32_OR (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_r600_hdmi.c236 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_avi_packet()
239 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_avi_packet()
350 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, in r600_set_vbi_packet()
371 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_audio_packet()
404 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in r600_set_mute()
458 WREG32_OR(HDMI0_CONTROL + offset, in r600_hdmi_update_audio_settings()
466 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_hdmi_update_audio_settings()
492 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); in r600_hdmi_enable()
500 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); in r600_hdmi_enable()
508 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); in r600_hdmi_enable()
H A Dradeon_dce3_1_afmt.c220 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in dce3_2_set_audio_packet()
224 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in dce3_2_set_audio_packet()
234 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in dce3_2_set_mute()
H A Dradeon_evergreen_hdmi.c389 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, in dce4_set_audio_packet()
400 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); in dce4_set_mute()
424 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
463 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
H A Dradeon_evergreen.c1755 WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY); in evergreen_hpd_set_polarity()
4651 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in evergreen_irq_ack()
4656 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in evergreen_irq_ack()
4661 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_ack()
H A Dradeon_si.c6187 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in si_irq_ack()
6192 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in si_irq_ack()
H A Dradeon.h2629 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vce_v3_0.c543 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); in vce_v3_0_mc_resume()
H A Damdgpu.h1084 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
H A Damdgpu_dce_v8_0.c1663 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, in dce_v8_0_afmt_setmode()
1671 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()