Searched refs:Vec64 (Results 1 – 4 of 4) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 278 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) { in SITargetLowering()
279 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
280 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
283 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
285 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
286 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
288 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
289 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
292 for (MVT Vec64 : { MVT::v4i64, MVT::v4f64 }) { in SITargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 362 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
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| H A D | HexagonISelLowering.cpp | 2675 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl, in contractPredicate() argument
2677 assert(ty(Vec64).getSizeInBits() == 64); in contractPredicate()
2678 if (isUndef(Vec64)) in contractPredicate()
2680 return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG); in contractPredicate()
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| H A D | HexagonISelLoweringHVX.cpp | 1013 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred() local
1015 {Vec64, DAG.getTargetConstant(0, dl, MVT::i32)}, DAG); in extractHvxSubvectorPred()
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