| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | AMDGPUInstructionSyntax.rst | 125 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
134 Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
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| H A D | AMDGPUUsage.rst | 11563 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
11567 * _e32 for 32-bit VOP1/VOP2/VOPC
11572 VOP1/VOP2/VOP3/VOPC examples:
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrFormats.td | 29 field bit VOP2 = 0;
155 let TSFlags{8} = VOP2;
223 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| H A D | VOP2Instructions.td | 10 // VOP2 Classes
76 let VOP2 = 1;
478 // VOP2 Instructions
942 //===------------------------------- VOP2 -------------------------------===//
988 //===------------------------- VOP2 (with name) -------------------------===//
1205 // VOP2 no carry-in, carry-out.
1213 // VOP2 carry-in, carry-out.
1626 // are VOP2 on SI and VOP3 on VI.
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| H A D | SIInstrInfo.h | 420 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
424 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| H A D | SIDefines.h | 33 VOP2 = 1 << 8, enumerator
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| H A D | SIInstrInfo.td | 1431 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1594 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1634 // VOP2 without modifiers
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| H A D | VOPInstructions.td | 818 def VOP2InfoTable : VOPInfoTable<"VOP2">;
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| H A D | SIInstructions.td | 880 // VOP2 Patterns
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX1011.rst | 56 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX906.rst | 36 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX908.rst | 56 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX7.rst | 720 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX8.rst | 869 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX9.rst | 1053 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX90a.rst | 964 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX10.rst | 1425 VOP2 section in Instructions
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3244 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
3785 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
8089 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
8093 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true); in cvtSdwaVOP2b()
8097 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true); in cvtSdwaVOP2e()
8129 if (BasicInstType == SIInstrFlags::VOP2 && in cvtSDWA()
8166 case SIInstrFlags::VOP2: in cvtSDWA()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 379 ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) { in printVOPDst()
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