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Searched refs:VGT_DEBUG_REG33__tess_topology_p0_q_MASK (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h12122 #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0x0c000000L macro
H A Dgfx_7_2_sh_mask.h18015 #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 macro
H A Dgfx_8_1_sh_mask.h20875 #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 macro
H A Dgfx_8_0_sh_mask.h20273 #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 macro