Searched refs:VECTOR_REVERSE (Results 1 – 8 of 8) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 548 VECTOR_REVERSE, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 294 case ISD::VECTOR_REVERSE: return "vector_reverse"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 947 case ISD::VECTOR_REVERSE: in SplitVectorResult()
5574 Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, InHi.getValueType(), InHi); in SplitVecRes_VECTOR_REVERSE()
5575 Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, InLo.getValueType(), InLo); in SplitVecRes_VECTOR_REVERSE()
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| H A D | LegalizeIntegerTypes.cpp | 99 case ISD::VECTOR_REVERSE: in PromoteIntegerResult()
4707 return DAG.getNode(ISD::VECTOR_REVERSE, dl, OutVT, V0); in PromoteIntRes_VECTOR_REVERSE()
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| H A D | SelectionDAGBuilder.cpp | 11039 setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V)); in visitVectorReverse()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 528 setOperationAction(ISD::VECTOR_REVERSE, VT, Custom); in RISCVTargetLowering()
588 setOperationAction(ISD::VECTOR_REVERSE, VT, Custom); in RISCVTargetLowering()
2306 case ISD::VECTOR_REVERSE: in LowerOperation()
4001 Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, LoVT, Lo); in lowerVECTOR_REVERSE()
4002 Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, HiVT, Hi); in lowerVECTOR_REVERSE()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 663 def vector_reverse : SDNode<"ISD::VECTOR_REVERSE", SDTVecReverse>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3841 return DAG.getNode(ISD::VECTOR_REVERSE, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
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