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Searched refs:VECTOR_REG_CAST (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.h140 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register enumerator
H A DARMISelLowering.cpp1675 MAKE_CASE(ARMISD::VECTOR_REG_CAST) in getTargetNodeName()
4004 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7866 Src.ShuffleVec = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
7918 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle); in ReconstructShuffle()
9639 PassThru.getOpcode() == ARMISD::VECTOR_REG_CAST) && in LowerMLOAD()
13158 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0); in PerformMVEVMULLCombine()
13159 SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1); in PerformMVEVMULLCombine()
13165 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0); in PerformMVEVMULLCombine()
13166 SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1); in PerformMVEVMULLCombine()
13984 BV.getOpcode() == ARMISD::VECTOR_REG_CAST) && in PerformVMOVRRDCombine()
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H A DARMInstrInfo.td305 // 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a
308 // the _memory_ storage format of the vector, whereas VECTOR_REG_CAST
312 // For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of
317 // VECTOR_REG_CAST emits no code at all if the vector is already in a register.
318 def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>;
320 // In little-endian, VECTOR_REG_CAST is often turned into bitconvert during
322 // that needs to match something that's _logically_ a VECTOR_REG_CAST must
326 // matches VECTOR_REG_CAST in either endianness, and also bitconvert in the