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Searched refs:VCE_UENC_REG_CLOCK_GATING (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_vce_v2_0.c56 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
58 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
72 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
74 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
98 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
101 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
169 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
H A Dradeon_vce_v1_0.c121 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
123 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
134 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
136 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
157 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_init_cg()
159 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_init_cg()
229 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume()
H A Dsid.h1909 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 macro
H A Dcikd.h2134 #define VCE_UENC_REG_CLOCK_GATING 0x207c0 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h1971 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 macro