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Searched refs:V128 (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td25 defm "" : ARGUMENT<V128, v16i8>;
26 defm "" : ARGUMENT<V128, v8i16>;
27 defm "" : ARGUMENT<V128, v4i32>;
28 defm "" : ARGUMENT<V128, v2i64>;
29 defm "" : ARGUMENT<V128, v4f32>;
30 defm "" : ARGUMENT<V128, v2f64>;
140 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
145 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
164 SIMD_I<(outs V128:$dst),
171 SIMD_I<(outs V128:$dst),
[all …]
H A DWebAssemblyRegisterInfo.td66 def V128 : WebAssemblyRegClass<[v4f32, v2f64, v2i64, v4i32, v16i8, v8i16], 128,
H A DWebAssemblyMCInstLower.cpp220 return wasm::ValType::V128; in getType()
H A DWebAssemblyAsmPrinter.cpp121 case wasm::ValType::V128: in getInvokeSig()
H A DWebAssemblyInstrInfo.td341 defm "" : LOCAL<V128, global_op32>, Requires<[HasSIMD128]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4860 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
4866 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
5344 def v16i8 : BaseSIMDThreeSameVectorPseudo<V128,
5345 [(set (v16i8 V128:$dst),
5346 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
5347 (v16i8 V128:$Rm)))]>;
5362 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
5363 (v8i16 V128:$RHS))),
5365 V128:$LHS, V128:$MHS, V128:$RHS)>;
5366 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
[all …]
H A DAArch64InstrInfo.td899 (AArch64duplane32 (v4i32 V128:$Rm),
906 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;
937 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
938 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
940 def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
941 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
967 def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
968 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
970 def : Pat<(v2i64 (int_aarch64_crypto_xar (v2i64 V128:$Vn), (v2i64 V128:$Vm), (i64 timm0_63:$imm))),
971 (XAR (v2i64 V128:$Vn), (v2i64 V128:$Vm), (timm0_63:$imm))>;
[all …]
H A DAArch64InstrGISel.td255 (FCVTNv2i32 (SCVTFv2f64 V128:$src))>;
257 (FCVTNv2i32 (UCVTFv2f64 V128:$src))>;
264 (XTNv2i32 (FCVTZSv2f64 V128:$src))>;
266 (XTNv2i32 (FCVTZUv2f64 V128:$src))>;
H A DAArch64RegisterInfo.td511 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp32 return wasm::ValType::V128; in parseType()
54 .Case("v128", WebAssembly::BlockType::V128) in parseBlockType()
143 return wasm::ValType::V128; in toValType()
H A DWebAssemblyTypeUtilities.h33 V128 = unsigned(wasm::ValType::V128), enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/
H A DWasm.h397 V128 = WASM_TYPE_V128, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/ObjectYAML/
H A DWasmYAML.cpp586 ECase(V128); in enumeration()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/
H A Daarch64-sve.md2539 (match_operand:<V128> 1 "register_operand" "w")))]
2551 ;; terms as a reverse of the V128 vector followed by a duplicate.
2555 (vec_select:<V128>
2556 (match_operand:<V128> 1 "register_operand" "w")
2561 GET_MODE_NUNITS (<V128>mode) - 1)"
2589 (match_operand:<V128> 1 "aarch64_sve_ld1rq_operand" "UtQ")]
2765 operands[1] = gen_rtx_REG (<V128>mode, REGNO (operands[1]));
2800 operands[1] = gen_rtx_REG (<V128>mode, REGNO (operands[1]));
8306 ;; The vec_select:<V128> sets memory lane number N of the V128 to lane
8312 ;; V128 (and thus lane number op2 + N of op1) to lane numbers N + I * STEP
[all …]
H A Diterators.md1138 (define_mode_attr V128 [(VNx16QI "V16QI")
/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/
H A Daarch64-sve.md2539 (match_operand:<V128> 1 "register_operand" "w")))]
2551 ;; terms as a reverse of the V128 vector followed by a duplicate.
2555 (vec_select:<V128>
2556 (match_operand:<V128> 1 "register_operand" "w")
2561 GET_MODE_NUNITS (<V128>mode) - 1)"
2589 (match_operand:<V128> 1 "aarch64_sve_ld1rq_operand" "UtQ")]
2765 operands[1] = gen_rtx_REG (<V128>mode, REGNO (operands[1]));
2800 operands[1] = gen_rtx_REG (<V128>mode, REGNO (operands[1]));
8689 ;; The vec_select:<V128> sets memory lane number N of the V128 to lane
8695 ;; V128 (and thus lane number op2 + N of op1) to lane numbers N + I * STEP
[all …]
H A Diterators.md1394 (define_mode_attr V128 [(VNx16QI "V16QI")
/netbsd-src/external/gpl3/gcc/dist/gcc/
H A DChangeLog-202036616 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
H A DChangeLog-201833079 (Vesize, V128, v128, Vewtype, V_FP_EQUIV, v_fp_equiv, VPRED): New