| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiTargetTransformInfo.h | 102 case ISD::UREM:
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| H A D | LanaiISelLowering.cpp | 111 setOperationAction(ISD::UREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1279 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1283 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1287 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1291 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1296 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1300 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1304 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1308 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1809 case ISD::UREM: in maybeLoweredToCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 272 ISD == ISD::UREM) && in getArithmeticInstrCost()
344 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
364 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
388 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
405 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
424 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
428 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 238 UREM, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1933 case ISD::UREM: in selectDivRem()
1950 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2055 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2056 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
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| H A D | MipsSEISelLowering.cpp | 243 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
290 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
348 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
2063 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 371 case ISD::UREM: in LegalizeOp()
901 case ISD::UREM: in Expand()
1444 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
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| H A D | SelectionDAGBuilder.h | 695 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
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| H A D | SelectionDAGDumper.cpp | 237 case ISD::UREM: return "urem"; in getOperationName()
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| H A D | FastISel.cpp | 507 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
1704 return selectBinaryOp(I, ISD::UREM); in selectOperator()
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| H A D | LegalizeDAG.cpp | 3252 case ISD::UREM: in ExpandNode()
4307 case ISD::UREM: in ConvertNodeToLibcall()
4491 case ISD::UREM: in PromoteNode()
4511 case ISD::UREM: in PromoteNode()
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| H A D | TargetLowering.cpp | 3872 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() && in SimplifySetCC()
4308 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && in SimplifySetCC()
4315 if (N0.getOpcode() == ISD::UREM) { in SimplifySetCC()
6512 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
6527 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
6592 SDValue ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Op1, BitWidthC); in expandROT()
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| H A D | SelectionDAG.cpp | 3385 case ISD::UREM: { in computeKnownBits()
5076 case ISD::UREM: in FoldValue()
5117 case ISD::UREM: { in isUndef()
5563 case ISD::UREM: in getNode()
5898 case ISD::UREM: in getNode()
5920 case ISD::UREM: in getNode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 134 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
140 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | ExtendingLLVM.rst | 112 legal operations. The case for ``ISD::UREM`` for expanding a remainder into
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 913 case ISD::UREM: in canOpTrap()
1764 case URem: return ISD::UREM; in InstructionOpcodeToISD()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 106 setOperationAction(ISD::UREM, VT, Expand); in BPFTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 147 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
148 setOperationAction(ISD::UREM, MVT::i16, Expand); in AVRTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 211 setOperationAction(ISD::UREM, XLenVT, Expand); in RISCVTargetLowering()
219 setOperationAction(ISD::UREM, MVT::i8, Custom); in RISCVTargetLowering()
222 setOperationAction(ISD::UREM, MVT::i16, Custom); in RISCVTargetLowering()
225 setOperationAction(ISD::UREM, MVT::i32, Custom); in RISCVTargetLowering()
689 setOperationAction(ISD::UREM, VT, Custom); in RISCVTargetLowering()
2364 case ISD::UREM: in LowerOperation()
4577 case ISD::UREM: in getRISCVWOpcode()
4751 case ISD::UREM: { in ReplaceNodeResults()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 508 setTargetDAGCombine(ISD::UREM); in NVPTXTargetLowering()
4515 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
4742 case ISD::UREM: in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4536 case ISD::UREM: in selectRem()
5033 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
5034 return selectRem(I, ISD::UREM); in fastSelectInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 363 setOperationAction(ISD::UREM, VT, Expand); in AMDGPUTargetLowering()
439 setOperationAction(ISD::UREM, VT, Expand); in AMDGPUTargetLowering()
1942 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 304 setOperationAction(ISD::UREM, MVT::i32, Legal); in PPCTargetLowering()
306 setOperationAction(ISD::UREM, MVT::i64, Legal); in PPCTargetLowering()
309 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
311 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
790 setOperationAction(ISD::UREM, VT, Expand); in PPCTargetLowering()
910 setOperationAction(ISD::UREM, MVT::v2i64, Legal); in PPCTargetLowering()
912 setOperationAction(ISD::UREM, MVT::v4i32, Legal); in PPCTargetLowering()
914 setOperationAction(ISD::UREM, MVT::v1i128, Legal); in PPCTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1584 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1631 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
|