| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 249 UDIVREM, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 155 setOperationAction(ISD::UDIVREM, MVT::i8, Custom); in AVRTargetLowering()
156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom); in AVRTargetLowering()
157 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AVRTargetLowering()
420 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
809 case ISD::UDIVREM: in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 95 UDIVREM, enumerator
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| H A D | SystemZOperators.td | 281 def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>;
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| H A D | SystemZISelLowering.cpp | 175 setOperationAction(ISD::UDIVREM, VT, Custom); in SystemZTargetLowering()
3602 lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM, in lowerUDIVREM()
5411 case ISD::UDIVREM: in LowerOperation()
5600 OPCODE(UDIVREM); in getTargetNodeName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 199 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
206 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
239 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
286 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
460 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, in LowerOperation()
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| H A D | MipsISelLowering.cpp | 498 setTargetDAGCombine(ISD::UDIVREM); in MipsTargetLowering()
1161 case ISD::UDIVREM: in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 133 setOperationAction(ISD::UDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
139 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 241 case ISD::UDIVREM: return "udivrem"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 373 case ISD::UDIVREM: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 4054 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_UDIV()
4055 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_UDIV()
4081 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_UREM()
4082 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_UREM()
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| H A D | LegalizeDAG.cpp | 3260 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
4326 case ISD::UDIVREM: in ConvertNodeToLibcall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 104 setOperationAction(ISD::UDIVREM, VT, Expand); in BPFTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 367 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
443 setOperationAction(ISD::UDIVREM, VT, Expand); in AMDGPUTargetLowering()
1242 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
1792 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2081 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
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| H A D | R600ISelLowering.cpp | 664 case ISD::UDIVREM: { in ReplaceNodeResults()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 109 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1585 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1631 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1501 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1508 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1811 case ISD::UDIVREM: in maybeLoweredToCall()
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| H A D | ARMISelLowering.cpp | 215 setOperationAction(ISD::UDIVREM, VT, Expand); in addTypeForNEON()
290 setOperationAction(ISD::UDIVREM, VT, Expand); in addMVEVectorTypes()
1248 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in ARMTargetLowering()
1250 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in ARMTargetLowering()
1253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in ARMTargetLowering()
9939 case ISD::UDIVREM: return LowerDivRem(Op, DAG); in LowerOperation()
10010 case ISD::UDIVREM: in ReplaceNodeResults()
18676 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemLibcall()
18694 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemArgList()
18721 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 129 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 163 setOperationAction(ISD::UDIVREM, IntVT, Expand); in initSPUActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 85 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 379 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 325 setOperationAction(ISD::UDIVREM, VT, Expand); in AArch64TargetLowering()
537 setOperationAction(ISD::UDIVREM, VT, Expand); in AArch64TargetLowering()
541 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
542 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
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