| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 624 unsigned TrueReg = in simplifyCode() local
626 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
628 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
687 unsigned TrueReg = in simplifyCode() local
689 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
691 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
|
| H A D | PPCInstrInfo.cpp | 1533 Register DstReg, Register TrueReg, in canInsertSelect() argument
1547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1572 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
1580 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1632 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1633 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3108 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3115 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3117 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3119 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
|
| H A D | PPCInstrInfo.h | 428 ArrayRef<MachineOperand> Cond, Register TrueReg,
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 787 auto TrueReg = MIB.getReg(2); in selectSelect() local
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
794 .addUse(TrueReg) in selectSelect()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 916 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
917 if (TrueReg == 0) in selectSelect()
925 std::swap(TrueReg, FalseReg); in selectSelect()
963 .addReg(TrueReg) in selectSelect()
|
| H A D | WebAssemblyISelLowering.cpp | 409 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
415 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
449 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
453 .addReg(TrueReg) in LowerFPToInt()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 535 Register DstReg, Register TrueReg, in canInsertSelect() argument
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
571 Register TrueReg, in insertSelect() argument
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
593 TrueReg = TReg; in insertSelect()
605 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
|
| H A D | SystemZInstrInfo.h | 243 ArrayRef<MachineOperand> Cond, Register TrueReg,
|
| H A D | SystemZISelLowering.cpp | 7132 Register TrueReg = MI->getOperand(1).getReg(); in createPHIsForSelects() local
7139 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
7141 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end()) in createPHIsForSelects()
7142 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
7149 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
7153 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
|
| H A D | SIInstrInfo.cpp | 1048 Register TrueReg, in insertVectorSelect() argument
1064 .addReg(TrueReg) in insertVectorSelect()
1079 .addReg(TrueReg) in insertVectorSelect()
1093 .addReg(TrueReg) in insertVectorSelect()
1107 .addReg(TrueReg) in insertVectorSelect()
1119 .addReg(TrueReg) in insertVectorSelect()
1139 .addReg(TrueReg) in insertVectorSelect()
1157 .addReg(TrueReg) in insertVectorSelect()
2494 Register DstReg, Register TrueReg, in canInsertSelect() argument
2501 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 863 Register TrueReg, Register FalseReg, in canInsertSelect() argument
887 Register TrueReg, Register FalseReg) const { in insertSelect() argument
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 218 ArrayRef<MachineOperand> Cond, Register TrueReg,
|
| H A D | AArch64InstrInfo.cpp | 613 Register DstReg, Register TrueReg, in canInsertSelect() argument
620 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
640 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
664 Register TrueReg, Register FalseReg) const { in insertSelect() argument
767 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
772 TrueReg = FalseReg; in insertSelect()
786 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
791 .addReg(TrueReg) in insertSelect()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 351 ArrayRef<MachineOperand> Cond, Register TrueReg,
|
| H A D | X86InstrInfo.cpp | 3308 Register DstReg, Register TrueReg, in canInsertSelect() argument
3323 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3346 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
3356 .addReg(TrueReg) in insertSelect()
|