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Searched refs:TruePred (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td53 MCReturnStatement<TruePred>>,
56 MCReturnStatement<TruePred>>],
69 MCReturnStatement<TruePred>>,
72 MCReturnStatement<TruePred>>],
90 MCReturnStatement<TruePred>>,
93 MCReturnStatement<TruePred>>],
128 MCReturnStatement<TruePred>>,
154 MCReturnStatement<TruePred>>],
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp1255 BasicBlock *TruePred = nullptr, *FalsePred = nullptr; in SimplifyUsingControlFlow() local
1259 TruePred = Pred; in SimplifyUsingControlFlow()
1263 assert(TruePred && FalsePred && "Must be!"); in SimplifyUsingControlFlow()
1277 BasicBlockEdge TrueIncEdge(TruePred, BB); in SimplifyUsingControlFlow()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ScheduleBdVer2.td1342 SchedVar<MCSchedPredicate<TruePred>, [WriteALU]>
1349 SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]>
1360 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]>
1366 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]>
1373 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]>
1383 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]>
H A DX86ScheduleBtVer2.td1047 ], TruePred >
H A DX86ScheduleZnver3.td1511 ], TruePred >
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td78 def TruePred : MCTrue;
154 // Otherwise, it simply evaluates to TruePred.
H A DTargetSchedule.td381 def NoSchedPred : MCSchedPredicate<TruePred>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp3451 BasicBlock *TruePred = QTB ? QTB : QFB->getSinglePredecessor(); in mergeConditionalStoreToAddress() local
3453 SplitBlockPredecessors(PostBB, {QFB, TruePred}, "condstore.split", DTU); in mergeConditionalStoreToAddress()