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Searched refs:Tmp2 (Results 1 – 24 of 24) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp65 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
75 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
82 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
104 Value* Tmp2 = Builder.CreateLShr(V, in LowerBSWAP() local
130 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
137 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
139 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp364 SDValue Tmp2 = Val; in PerformInsertVectorEltInMemory() local
388 Ch, dl, Tmp2, StackPtr2, in PerformInsertVectorEltInMemory()
1653 SDValue Tmp2 = SDValue(Node, 1); in ExpandDYNAMIC_STACKALLOC() local
1661 SDValue Size = Tmp2.getOperand(1); in ExpandDYNAMIC_STACKALLOC()
1677 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true), in ExpandDYNAMIC_STACKALLOC()
1681 Results.push_back(Tmp2); in ExpandDYNAMIC_STACKALLOC()
2670 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
2921 if (TLI.expandUINT_TO_FP(Node, Tmp1, Tmp2, DAG)) { in ExpandNode()
2924 Results.push_back(Tmp2); in ExpandNode()
2930 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Tmp2))) { in ExpandNode()
[all …]
H A DSelectionDAG.cpp2104 SDValue Tmp2 = Node->getOperand(1); in expandVAArg() local
2108 Tmp2, MachinePointerInfo(V)); in expandVAArg()
2127 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); in expandVAArg()
3680 unsigned Tmp, Tmp2; in ComputeNumSignBits() local
3711 Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1); in ComputeNumSignBits()
3718 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1); in ComputeNumSignBits()
3720 Tmp = std::min(Tmp, Tmp2); in ComputeNumSignBits()
3747 Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedRHS, Depth + 1); in ComputeNumSignBits()
3748 Tmp = std::min(Tmp, Tmp2); in ComputeNumSignBits()
3788 Tmp2 = VTBits; in ComputeNumSignBits()
[all …]
H A DTargetLowering.cpp6629 SDValue Tmp2, Tmp3; in expandShiftParts() local
6631 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
6634 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
6647 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
6650 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
7177 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
7187 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
7191 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT)); in expandBSWAP()
7193 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); in expandBSWAP()
7194 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); in expandBSWAP()
[all …]
H A DLegalizeFloatTypes.cpp1820 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
1824 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo, in FloatExpandSetCCOperands()
1826 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
1827 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1832 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, in FloatExpandSetCCOperands()
1834 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
1835 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3733 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3734 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
3736 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
3769 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3770 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
3771 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
3802 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
3803 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
3804 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4070 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1809 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareMBB() local
1821 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
1826 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
1837 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
1841 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
1873 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() local
1882 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
1887 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
1891 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() local
1902 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp132 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend); in generateSignedDivisionCode() local
133 Value *U_Dvnd = Builder.CreateSub(Tmp2, Tmp); in generateSignedDivisionCode()
272 Value *Tmp2 = Builder.CreateSub(MSB, SR); in generateUnsignedDivisionCode() local
273 Value *Q = Builder.CreateShl(Dividend, Tmp2); in generateUnsignedDivisionCode()
/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
H A DExprEngineC.cpp49 ExplodedNodeSet Tmp2; in VisitBinaryOperator() local
74 evalStore(Tmp2, B, LHS, *it, state->BindExpr(B, LCtx, ExprVal), in VisitBinaryOperator()
80 StmtNodeBuilder Bldr(*it, Tmp2, *currBldrCtx); in VisitBinaryOperator()
188 evalStore(Tmp2, B, LHS, *I, state, location, LHSVal); in VisitBinaryOperator()
193 getCheckerManager().runCheckersForPostStmt(Dst, Tmp2, B, *this); in VisitBinaryOperator()
H A DCheckerManager.cpp125 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
133 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1959 SmallVector<MachineOperand,1> Tmp2; in createPreheaderForLoop() local
1967 Tmp2.clear(); in createPreheaderForLoop()
1968 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false); in createPreheaderForLoop()
1971 if (TB != Header && (Tmp2.empty() || FB != Header)) in createPreheaderForLoop()
1980 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); in createPreheaderForLoop()
H A DHexagonSplitDouble.cpp691 auto *Tmp2 = in splitMemRef() local
693 HighI->addMemOperand(MF, Tmp2); in splitMemRef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DValueTracking.cpp2880 unsigned Tmp, Tmp2; in ComputeNumSignBitsImpl() local
2965 Tmp2 = ShAmt->getZExtValue(); in ComputeNumSignBitsImpl()
2966 return Tmp - Tmp2; in ComputeNumSignBitsImpl()
2976 Tmp2 = ComputeNumSignBits(U->getOperand(1), Depth + 1, Q); in ComputeNumSignBitsImpl()
2977 FirstAnswer = std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
2994 Tmp2 = ComputeNumSignBits(U->getOperand(2), Depth + 1, Q); in ComputeNumSignBitsImpl()
2995 return std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
3021 Tmp2 = ComputeNumSignBits(U->getOperand(1), Depth + 1, Q); in ComputeNumSignBitsImpl()
3022 if (Tmp2 == 1) break; in ComputeNumSignBitsImpl()
3023 return std::min(Tmp, Tmp2) - 1; in ComputeNumSignBitsImpl()
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGExprComplex.cpp856 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d in EmitBinDiv() local
857 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1985 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts() local
1986 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2045 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts() local
2046 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
2398 SDValue Tmp2 = ST->getBasePtr(); in LowerSTOREi1() local
2403 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1901 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFrint() local
1907 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
3139 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X); in legalizeFastUnsafeFDIV64() local
3141 B.buildFMA(Res, Tmp2, R, Ret); in legalizeFastUnsafeFDIV64()
H A DAMDGPUISelLowering.cpp2196 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC() local
2198 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2214 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT() local
2225 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFRINT()
H A DSIISelLowering.cpp3273 SDValue Tmp2 = Op.getValue(1); in lowerDYNAMIC_STACKALLOCImpl() local
3283 SDValue Size = Tmp2.getOperand(1); in lowerDYNAMIC_STACKALLOCImpl()
3307 Tmp2 = DAG.getCALLSEQ_END( in lowerDYNAMIC_STACKALLOCImpl()
3311 return DAG.getMergeValues({Tmp1, Tmp2}, dl); in lowerDYNAMIC_STACKALLOCImpl()
8296 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X); in lowerFastUnsafeFDIV64() local
8297 return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret); in lowerFastUnsafeFDIV64()
9876 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine() local
9879 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3); in performIntMed3ImmCombine()
H A DSIInstrInfo.cpp571 Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); in indirectCopyToAGPR() local
572 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
574 Tmp = Tmp2; in indirectCopyToAGPR()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp7429 Register Tmp2 = MRI.createVirtualRegister(RC); in emitAtomicLoadBinary() local
7430 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp); in emitAtomicLoadBinary()
7432 .addReg(Tmp2).addImm(-1); in emitAtomicLoadBinary()
7712 Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass); in emitPair128() local
7715 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2) in emitPair128()
7718 .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64); in emitPair128()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5785 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
5787 SDValue(Tmp2, 0))); in Select()
5799 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
5801 SDValue(Tmp2, 0))); in Select()
H A DPPCISelLowering.cpp8736 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS() local
8738 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
8765 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS() local
8767 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
8793 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRA_PARTS() local
8795 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp3963 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32); in Select() local
3964 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; in Select()
H A DARMISelLowering.cpp6034 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts() local
6035 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
6074 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts() local
6075 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()