| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 39 bool TargetSchedModel::hasInstrSchedModel() const { in hasInstrSchedModel()
43 bool TargetSchedModel::hasInstrItineraries() const { in hasInstrItineraries()
63 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) { in init()
85 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI, in mustBeginGroup()
96 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI, in mustEndGroup()
107 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, in getNumMicroOps()
132 const MCSchedClassDesc *TargetSchedModel::
184 unsigned TargetSchedModel::computeOperandLatency( in computeOperandLatency()
256 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { in computeInstrLatency()
260 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const { in computeInstrLatency()
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| H A D | MachineTraceMetrics.cpp | 126 for (TargetSchedModel::ProcResIter in getResources()
894 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards()
955 const TargetSchedModel &SchedModel, in pushDepHeight()
1241 for (TargetSchedModel::ProcResIter in getResourceLength()
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| H A D | MachineScheduler.cpp | 2020 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init()
2029 for (TargetSchedModel::ProcResIter in init()
2040 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) { in init()
2443 for (TargetSchedModel::ProcResIter in bumpNode()
2456 for (TargetSchedModel::ProcResIter in bumpNode()
2624 const TargetSchedModel *SchedModel) { in initResourceDelta()
2629 for (TargetSchedModel::ProcResIter in initResourceDelta()
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| H A D | MachineCombiner.cpp | 78 TargetSchedModel TSchedModel;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.h | 41 const TargetSchedModel *SchedModel;
51 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM) in VLIWResourceModel()
135 const TargetSchedModel *SchedModel = nullptr;
165 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { in init()
218 const TargetSchedModel *SchedModel = nullptr;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.h | 48 const TargetSchedModel *SchedModel;
111 const TargetSchedModel *SM) in SystemZHazardRecognizer()
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| H A D | SystemZHazardRecognizer.cpp | 175 for (TargetSchedModel::ProcResIter in dumpSU()
296 for (TargetSchedModel::ProcResIter in EmitInstruction()
400 for (TargetSchedModel::ProcResIter in resourcesCost()
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| H A D | SystemZMachineScheduler.h | 38 TargetSchedModel SchedModel;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetSchedule.h | 31 class TargetSchedModel {
50 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {} in TargetSchedModel() function
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| H A D | TargetSubtargetInfo.h | 50 class TargetSchedModel; variable
142 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
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| H A D | MachineScheduler.h | 602 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
618 const TargetSchedModel *SchedModel = nullptr;
699 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
903 const TargetSchedModel *SchedModel);
908 const TargetSchedModel *SchedModel = nullptr;
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| H A D | ScheduleDAGInstrs.h | 125 TargetSchedModel SchedModel;
262 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel()
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| H A D | MachineTraceMetrics.h | 93 TargetSchedModel SchedModel;
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| H A D | TargetInstrInfo.h | 61 class TargetSchedModel; variable
1625 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()
1635 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.h | 50 TargetSchedModel TSchedModel;
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| H A D | AMDGPUSubtarget.cpp | 935 const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel(); in apply()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 34 TargetSchedModel SchedModel;
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| H A D | AArch64Schedule.td | 10 // const MachineInstr *MI and const TargetSchedModel *SchedModel
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| H A D | AArch64SIMDInstrOpt.cpp | 71 TargetSchedModel SchedModel;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86PadShortFunction.cpp | 94 TargetSchedModel TSM;
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| H A D | X86InstrInfo.h | 487 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
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| H A D | X86CmovConversion.cpp | 118 TargetSchedModel TSchedModel;
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| H A D | X86FixupLEAs.cpp | 124 TargetSchedModel TSM;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 459 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
464 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 326 bool hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
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