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Searched refs:TIMING_3D_FORMAT_TOP_AND_BOTTOM (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/modules/info_packet/
H A Damdgpu_info_packet.c235 case TIMING_3D_FORMAT_TOP_AND_BOTTOM: in mod_build_vsc_infopacket()
496 case TIMING_3D_FORMAT_TOP_AND_BOTTOM: in mod_build_hf_vsif_infopacket()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_hw_types.h695 TIMING_3D_FORMAT_TOP_AND_BOTTOM, enumerator
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_optc.c534 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && in optc1_validate_timing()
H A Damdgpu_dcn10_hw_sequencer.c1413 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { in patch_address_for_sbs_tb_stereo()
2781 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) in dcn10_config_stereo_parameters()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
H A Damdgpu_dcn_calcs.c1219 TIMING_3D_FORMAT_TOP_AND_BOTTOM || in dcn_validate_bandwidth()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_hwseq.c1923 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { in patch_address_for_sbs_tb_stereo()
H A Damdgpu_dcn20_resource.c2527 TIMING_3D_FORMAT_TOP_AND_BOTTOM || in dcn20_validate_apply_pipe_split_flags()