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Searched refs:SrcR (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp469 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
471 unsigned SrcR, InsR; member
487 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
534 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
687 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm()
881 unsigned SrcR = *I; in findRecordInsertForms() local
883 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
916 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
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H A DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
49 assert(Register::isPhysicalRegister(SrcR.Reg)); in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
H A DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
114 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonFrameLowering.cpp1757 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1759 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1781 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1791 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1844 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1860 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1931 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1932 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2()
1933 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2()
2031 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
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H A DHexagonBitSimplify.cpp2220 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
2229 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) in genBitSplit()
2248 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) in genBitSplit()
2265 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) in genBitSplit()
2280 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) in genBitSplit()
2282 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) in genBitSplit()
2292 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) in genBitSplit()
2311 .addReg(SrcR, 0, SrcSR) in genBitSplit()
H A DHexagonConstPropagation.cpp1949 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
1950 bool Eval = evaluateCOPY(SrcR, Inputs, RC); in evaluate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp536 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA() local
538 .add(SrcR) in processInstructionForSlowLEA()