| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 997 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
1004 assert(SrcOps.size() == 3 && "Invalid select"); in buildInstr()
1006 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
1007 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); in buildInstr()
1014 assert(SrcOps.size() == 1 && "Invalid Srcs"); in buildInstr()
1016 SrcOps[0].getLLTTy(*getMRI())); in buildInstr()
1038 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
1040 SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
1041 SrcOps[1].getLLTTy(*getMRI())); in buildInstr()
1050 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
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| H A D | CSEMIRBuilder.cpp | 106 ArrayRef<SrcOp> SrcOps, in profileEverything() argument
114 profileSrcOps(SrcOps, B); in profileEverything()
169 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
188 assert(SrcOps.size() == 2 && "Invalid sources"); in buildInstr()
190 if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(), in buildInstr()
191 SrcOps[1].getReg(), *getMRI())) in buildInstr()
197 assert(SrcOps.size() == 2 && "Invalid src ops"); in buildInstr()
199 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
200 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
209 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.h | 73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
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| H A D | MachineIRBuilder.h | 1872 ArrayRef<SrcOp> SrcOps,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 57 SmallVector<SrcOp, 2> SrcOps; ///< Source registers. member
59 std::initializer_list<SrcOp> SrcOps) in ShuffleVectorPseudo()
60 : Opc(Opc), Dst(Dst), SrcOps(SrcOps){}; in ShuffleVectorPseudo()
399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
411 MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm()); in applyEXT()
413 {MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst}); in applyEXT()
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| H A D | AArch64InstructionSelector.cpp | 208 std::initializer_list<llvm::SrcOp> SrcOps,
4101 std::initializer_list<llvm::SrcOp> SrcOps, MachineIRBuilder &MIRBuilder, in emitInstr() argument
4106 auto MI = MIRBuilder.buildInstr(Opcode, DstOps, SrcOps); in emitInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22033 SmallVectorImpl<SDValue> &SrcOps, in matchScalarReduction() argument
22076 SrcOps.push_back(Src); in matchScalarReduction()
22088 for (SDValue &SrcOp : SrcOps) in matchScalarReduction()
36695 ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root, in combineX86ShufflesRecursively() argument
36712 SDValue Op = SrcOps[SrcOpIndex]; in combineX86ShufflesRecursively()
36791 Ops.append(SrcOps.begin(), SrcOps.end()); in combineX86ShufflesRecursively()
44541 SmallVector<SDValue, 2> SrcOps; in combineAnd() local
44543 if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps, &SrcPartials) && in combineAnd()
44544 SrcOps.size() == 1) { in combineAnd()
44547 unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements(); in combineAnd()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 19720 SmallVector<SDValue, 4> SrcOps; in combineConcatVectorOfCasts() local
19725 SrcOps.push_back(Op.getOperand(0)); in combineConcatVectorOfCasts()
19755 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatSrcVT, SrcOps); in combineConcatVectorOfCasts()
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