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Searched refs:Src1RC (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1592 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1594 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1599 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1628 Src1Mod:$src1_modifiers, Src1RC:$src1,
1631 Src1Mod:$src1_modifiers, Src1RC:$src1,
1636 (ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
1637 (ins Src0RC:$src0, Src1RC:$src1))
1646 Src1Mod:$src1_modifiers, Src1RC:$src1,
1651 Src1Mod:$src1_modifiers, Src1RC:$src1,
1655 Src1Mod:$src1_modifiers, Src1RC:$src1,
[all …]
H A DSIFixSGPRCopies.cpp684 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
687 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
690 TRI->hasVectorRegisters(Src1RC))) { in runOnMachineFunction()
H A DVOP1Instructions.td309 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
314 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
315 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
H A DSIInstrInfo.cpp6403 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalar64BitAddSub() local
6405 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6409 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub()
6415 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub()
6471 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
6475 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6479 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
6483 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
H A DAMDGPUInstructionSelector.cpp734 const TargetRegisterClass *Src1RC = in selectG_INSERT() local
740 if (!Src0RC || !Src1RC) in selectG_INSERT()
745 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
H A DSIISelLowering.cpp3968 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local
3975 TRI->getSubRegClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
3980 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
3985 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()