Searched refs:ShiftOffset (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPostLegalizerCombiner.cpp | 63 unsigned ShiftOffset; member
217 unsigned ShiftOffset = 8 * Offset; in matchCvtF32UByteN() local
219 ShiftOffset += ShiftAmt; in matchCvtF32UByteN()
221 ShiftOffset -= ShiftAmt; in matchCvtF32UByteN()
224 MatchInfo.ShiftOffset = ShiftOffset; in matchCvtF32UByteN()
225 return ShiftOffset < 32 && ShiftOffset >= 8 && (ShiftOffset % 8) == 0; in matchCvtF32UByteN()
235 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN()
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| H A D | SIISelLowering.cpp | 10777 unsigned ShiftOffset = 8 * Offset; in performCvtF32UByteNCombine() local
10779 ShiftOffset -= C->getZExtValue(); in performCvtF32UByteNCombine()
10781 ShiftOffset += C->getZExtValue(); in performCvtF32UByteNCombine()
10783 if (ShiftOffset < 32 && (ShiftOffset % 8) == 0) { in performCvtF32UByteNCombine()
10784 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + ShiftOffset / 8, SL, in performCvtF32UByteNCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1212 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, VT); in PromoteIntRes_FunnelShift() local
1213 Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset); in PromoteIntRes_FunnelShift()
1218 Amount = DAG.getNode(ISD::ADD, DL, VT, Amount, ShiftOffset); in PromoteIntRes_FunnelShift()
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