Searched refs:SelectCC (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1779 SDValue SelectCC = FNeg.getOperand(0); in PerformDAGCombine() local
1780 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1781 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1782 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1783 !isHWTrueValue(SelectCC.getOperand(2)) || in PerformDAGCombine()
1784 !isHWFalseValue(SelectCC.getOperand(3))) { in PerformDAGCombine()
1789 SelectCC.getOperand(0), // LHS in PerformDAGCombine()
1790 SelectCC.getOperand(1), // RHS in PerformDAGCombine()
1793 SelectCC.getOperand(4)); // CC in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 225 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3941 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, in SelectCC() function in PPCDAGToDAGISel
4418 SDValue CCReg = SelectCC(LHS, RHS, CC, dl, Chain); in trySETCC()
5404 SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl); in Select()
5430 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); in Select()
5618 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5877 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); in lowerFPTRUNC_F64_TO_F16() local
5880 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); in lowerFPTRUNC_F64_TO_F16()
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