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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
35 const MCSubtargetInfo &STI, raw_ostream &O);
37 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI,
45 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
48 const MCSubtargetInfo &STI, raw_ostream &O) { in printOperand() argument
49 printOperand(MI, OpNum, STI, O); in printOperand()
53 const MCSubtargetInfo &STI, raw_ostream &O);
55 const MCSubtargetInfo &STI, raw_ostream &O);
58 const MCSubtargetInfo &STI, raw_ostream &O);
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H A DARMTargetStreamer.cpp119 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) { in getArchForCPU() argument
120 if (STI.getCPU() == "xscale") in getArchForCPU()
123 if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
124 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
131 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
135 } else if (STI.hasFeature(ARM::HasV6T2Ops)) in getArchForCPU()
137 else if (STI.hasFeature(ARM::HasV8MBaselineOps)) in getArchForCPU()
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H A DARMMCCodeEmitter.cpp63 bool isThumb(const MCSubtargetInfo &STI) const { in isThumb()
64 return STI.getFeatureBits()[ARM::ModeThumb]; in isThumb()
67 bool isThumb2(const MCSubtargetInfo &STI) const { in isThumb2()
68 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; in isThumb2()
71 bool isTargetMachO(const MCSubtargetInfo &STI) const { in isTargetMachO()
72 const Triple &TT = STI.getTargetTriple(); in isTargetMachO()
82 const MCSubtargetInfo &STI) const;
88 const MCSubtargetInfo &STI) const;
95 const MCSubtargetInfo &STI) const;
100 const MCSubtargetInfo &STI) const;
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H A DARMInstPrinter.cpp92 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
106 printSBitModifierOperand(MI, 6, STI, O); in printInst()
107 printPredicateOperand(MI, 4, STI, O); in printInst()
128 printSBitModifierOperand(MI, 5, STI, O); in printInst()
129 printPredicateOperand(MI, 3, STI, O); in printInst()
153 printPredicateOperand(MI, 2, STI, O); in printInst()
157 printRegisterList(MI, 4, STI, O); in printInst()
167 printPredicateOperand(MI, 4, STI, O); in printInst()
182 printPredicateOperand(MI, 2, STI, O); in printInst()
186 printRegisterList(MI, 4, STI, O); in printInst()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O);
33 const MCSubtargetInfo &STI, raw_ostream &O) override;
39 const MCSubtargetInfo &STI, raw_ostream &O);
42 const MCSubtargetInfo &STI, raw_ostream &O);
47 const MCSubtargetInfo &STI, raw_ostream &O);
54 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
56 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
59 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
64 const MCSubtargetInfo &STI, raw_ostream &O);
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H A DAMDGPUInstPrinter.cpp50 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
53 printInstruction(MI, Address, STI, OS); in printInst()
58 const MCSubtargetInfo &STI, in printU4ImmOperand() argument
69 const MCSubtargetInfo &STI, in printU16ImmOperand() argument
77 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
96 const MCSubtargetInfo &STI, in printU32ImmOperand() argument
132 const MCSubtargetInfo &STI, in printOffset() argument
142 const MCSubtargetInfo &STI, in printFlatOffset() argument
155 if (AMDGPU::isGFX10Plus(STI)) { in printFlatOffset()
165 const MCSubtargetInfo &STI, in printOffset0() argument
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H A DSIMCCodeEmitter.cpp34 const MCSubtargetInfo &STI) const;
46 const MCSubtargetInfo &STI) const override;
51 const MCSubtargetInfo &STI) const override;
57 const MCSubtargetInfo &STI) const override;
61 const MCSubtargetInfo &STI) const override;
65 const MCSubtargetInfo &STI) const override;
69 const MCSubtargetInfo &STI) const override;
73 const MCSubtargetInfo &STI) const override;
100 static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI) { in getLit16IntEncoding() argument
105 static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) { in getLit16Encoding() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
35 const MCSubtargetInfo &STI, raw_ostream &O);
37 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI,
51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
56 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
58 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
68 const MCSubtargetInfo &STI, raw_ostream &O) { in printPostIncOperand() argument
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H A DAArch64MCCodeEmitter.cpp58 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
90 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const;
103 const MCSubtargetInfo &STI) const;
109 const MCSubtargetInfo &STI) const;
115 const MCSubtargetInfo &STI) const;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h35 bool isMicroMips(const MCSubtargetInfo &STI) const;
36 bool isMips32r6(const MCSubtargetInfo &STI) const;
47 void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
52 const MCSubtargetInfo &STI) const override;
58 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
86 const MCSubtargetInfo &STI) const;
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H A DMipsMCCodeEmitter.cpp120 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { in isMicroMips()
121 return STI.getFeatureBits()[Mips::FeatureMicroMips]; in isMicroMips()
124 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { in isMips32r6()
125 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in isMips32r6()
133 const MCSubtargetInfo &STI, in emitInstruction() argument
139 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { in emitInstruction()
140 emitInstruction(Val >> 16, 2, STI, OS); in emitInstruction()
141 emitInstruction(Val, 2, STI, OS); in emitInstruction()
155 const MCSubtargetInfo &STI) const in encodeInstruction()
183 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
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H A DMipsTargetStreamer.cpp37 static bool isMicroMips(const MCSubtargetInfo *STI) { in isMicroMips() argument
38 return STI->getFeatureBits()[Mips::FeatureMicroMips]; in isMicroMips()
135 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument
170 const MCSubtargetInfo *STI) { in emitR() argument
175 getStreamer().emitInstruction(TmpInst, *STI); in emitR()
179 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRX() argument
185 getStreamer().emitInstruction(TmpInst, *STI); in emitRX()
189 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRI() argument
190 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
194 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRR() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp91 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI) { in getHsaAbiVersion() argument
92 if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA) in getHsaAbiVersion()
108 bool isHsaAbiVersion2(const MCSubtargetInfo *STI) { in isHsaAbiVersion2() argument
109 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI)) in isHsaAbiVersion2()
114 bool isHsaAbiVersion3(const MCSubtargetInfo *STI) { in isHsaAbiVersion3() argument
115 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI)) in isHsaAbiVersion3()
120 bool isHsaAbiVersion4(const MCSubtargetInfo *STI) { in isHsaAbiVersion4() argument
121 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI)) in isHsaAbiVersion4()
126 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI) { in isHsaAbiVersion3Or4() argument
127 return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI); in isHsaAbiVersion3Or4()
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H A DAMDGPUBaseInfo.h40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
87 const MCSubtargetInfo &STI;
92 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
164 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
168 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.h36 const MCSubtargetInfo &STI, raw_ostream &O) override;
41 const MCSubtargetInfo &STI, raw_ostream &O);
45 const MCSubtargetInfo &STI, raw_ostream &OS);
48 const MCSubtargetInfo &STI, raw_ostream &OS);
50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
53 const MCSubtargetInfo &STI, raw_ostream &O,
56 const MCSubtargetInfo &STI, raw_ostream &O);
59 const MCSubtargetInfo &STI, raw_ostream &O);
61 const MCSubtargetInfo &STI, raw_ostream &O);
63 const MCSubtargetInfo &STI, raw_ostream &O);
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H A DPPCMCCodeEmitter.h40 const MCSubtargetInfo &STI) const;
43 const MCSubtargetInfo &STI) const;
46 const MCSubtargetInfo &STI) const;
49 const MCSubtargetInfo &STI) const;
52 const MCSubtargetInfo &STI) const;
55 const MCSubtargetInfo &STI,
59 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
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H A DPPCMCCodeEmitter.cpp45 const MCSubtargetInfo &STI) const { in getDirectBrEncoding()
49 return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
61 const MCSubtargetInfo &STI) const { in getCondBrEncoding()
63 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
74 const MCSubtargetInfo &STI) const { in getAbsDirectBrEncoding()
76 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
87 const MCSubtargetInfo &STI) const { in getAbsCondBrEncoding()
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
100 const MCSubtargetInfo &STI) const { in getVSRpEvenEncoding()
102 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getVSRpEvenEncoding()
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H A DPPCInstPrinter.cpp56 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
74 printOperand(MI, 0, STI, O); in printInst()
76 printOperand(MI, 2, STI, O); in printInst()
78 printOperand(MI, 1, STI, O); in printInst()
97 printInstruction(MI, Address, STI, O); in printInst()
127 printOperand(MI, 0, STI, O); in printInst()
129 printOperand(MI, 1, STI, O); in printInst()
144 printOperand(MI, 0, STI, O); in printInst()
146 printOperand(MI, 1, STI, O); in printInst()
170 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; in printInst()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp49 const MCSubtargetInfo &STI) const override;
55 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
81 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
87 const MCSubtargetInfo &STI) const;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVTargetStreamer.cpp40 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { in emitTargetAttributes() argument
41 if (STI.hasFeature(RISCV::FeatureRV32E)) in emitTargetAttributes()
47 if (STI.hasFeature(RISCV::Feature64Bit)) in emitTargetAttributes()
49 if (STI.hasFeature(RISCV::FeatureRV32E)) in emitTargetAttributes()
53 if (STI.hasFeature(RISCV::FeatureStdExtM)) in emitTargetAttributes()
55 if (STI.hasFeature(RISCV::FeatureStdExtA)) in emitTargetAttributes()
57 if (STI.hasFeature(RISCV::FeatureStdExtF)) in emitTargetAttributes()
59 if (STI.hasFeature(RISCV::FeatureStdExtD)) in emitTargetAttributes()
61 if (STI.hasFeature(RISCV::FeatureStdExtC)) in emitTargetAttributes()
63 if (STI.hasFeature(RISCV::FeatureStdExtB)) in emitTargetAttributes()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp52 const MCSubtargetInfo &STI);
54 const MCSubtargetInfo &STI);
56 const MCSubtargetInfo &STI);
84 const MCSubtargetInfo &STI) { in emitSIC() argument
88 OutStreamer.emitInstruction(SICInst, STI); in emitSIC()
92 const MCSubtargetInfo &STI) { in emitBSIC() argument
100 OutStreamer.emitInstruction(BSICInst, STI); in emitBSIC()
104 const MCSubtargetInfo &STI) { in emitLEAzzi() argument
112 OutStreamer.emitInstruction(LEAInst, STI); in emitLEAzzi()
116 const MCSubtargetInfo &STI) { in emitLEASLzzi() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp48 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
50 if (!printAliasInstr(MI, Address, STI, OS)) in printInst()
51 printInstruction(MI, Address, STI, OS); in printInst()
56 const MCSubtargetInfo &STI, raw_ostream &O) { in printOperand() argument
79 const MCSubtargetInfo &STI, in printMemASXOperand() argument
83 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
85 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand()
93 printOperand(MI, OpNum + 2, STI, O); in printMemASXOperand()
110 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand()
116 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
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H A DVEMCCodeEmitter.cpp54 const MCSubtargetInfo &STI) const override;
60 const MCSubtargetInfo &STI) const;
66 const MCSubtargetInfo &STI) const;
70 const MCSubtargetInfo &STI) const;
73 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) const { in encodeInstruction()
91 computeAvailableFeatures(STI.getFeatureBits())); in encodeInstruction()
93 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
102 const MCSubtargetInfo &STI) const { in getMachineOpValue()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { in isV9()
38 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; in isV9()
47 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
49 if (!printAliasInstr(MI, Address, STI, O) && in printInst()
50 !printSparcAliasInstr(MI, STI, O)) in printInst()
51 printInstruction(MI, Address, STI, O); in printInst()
56 const MCSubtargetInfo &STI, in printSparcAliasInstr() argument
77 O << "\tjmp "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr()
80 O << "\tcall "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr()
86 if (isV9(STI) in printSparcAliasInstr()
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H A DSparcMCCodeEmitter.cpp59 const MCSubtargetInfo &STI) const override;
65 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
74 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
80 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const;
86 const MCSubtargetInfo &STI) const;
99 const MCSubtargetInfo &STI) const { in encodeInstruction()
101 computeAvailableFeatures(STI.getFeatureBits())); in encodeInstruction()
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