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Searched refs:SPLAT_VECTOR (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp98 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
165 setOperationAction(ISD::SPLAT_VECTOR, T, Custom); in initializeHVXLowering()
269 setTargetDAGCombine(ISD::SPLAT_VECTOR); in initializeHVXLowering()
531 SDValue S = DAG.getNode(ISD::SPLAT_VECTOR, dl, WordTy, SplatV); in buildHvxVectorReg()
1162 SDValue True = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in extendHvxVectorPred()
1458 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1460 SDValue VecW = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1462 SDValue VecN1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
2092 case ISD::SPLAT_VECTOR: in LowerHvxOperation()
2256 if (Ops[0].getOpcode() == ISD::SPLAT_VECTOR) { in PerformHvxDAGCombine()
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H A DHexagonISelLowering.cpp1650 ISD::SPLAT_VECTOR, in HexagonTargetLowering()
1709 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); in HexagonTargetLowering()
2289 case ISD::SPLAT_VECTOR: in getVectorShiftByInt()
2412 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector32()
2473 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector64()
2691 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h584 SPLAT_VECTOR, enumerator
H A DSelectionDAG.h833 return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1339 if (N.getOpcode() != ISD::SPLAT_VECTOR && in selectVSplat()
1353 if ((N.getOpcode() != ISD::SPLAT_VECTOR && in selectVSplatSimmHelper()
1402 if ((N.getOpcode() != ISD::SPLAT_VECTOR && in selectVSplatUimm5()
H A DRISCVISelLowering.cpp436 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
464 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
553 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
669 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
2310 case ISD::SPLAT_VECTOR: in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp142 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
176 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
225 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
314 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicate()
2478 case ISD::SPLAT_VECTOR: in isSplatValue()
2616 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
5188 N1->getOpcode() == ISD::SPLAT_VECTOR; in FoldConstantArithmetic()
5192 N2->getOpcode() == ISD::SPLAT_VECTOR; in FoldConstantArithmetic()
5225 else if (N1->getOpcode() == ISD::SPLAT_VECTOR) in FoldConstantArithmetic()
5233 else if (N2->getOpcode() == ISD::SPLAT_VECTOR) in FoldConstantArithmetic()
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H A DSelectionDAGDumper.cpp292 case ISD::SPLAT_VECTOR: return "splat_vector"; in getOperationName()
H A DLegalizeVectorOps.cpp935 : ISD::SPLAT_VECTOR, in ExpandSELECT()
H A DLegalizeVectorTypes.cpp927 case ISD::SPLAT_VECTOR: in SplitVectorResult()
1662 StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi); in SplitVecRes_STEP_VECTOR()
1677 assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode"); in SplitVecRes_ScalarOp()
2987 case ISD::SPLAT_VECTOR: in WidenVectorResult()
H A DLegalizeIntegerTypes.cpp111 case ISD::SPLAT_VECTOR: in PromoteIntegerResult()
1497 case ISD::SPLAT_VECTOR: in PromoteIntegerOperand()
4198 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break; in ExpandIntegerOperand()
4783 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op); in PromoteIntRes_SPLAT_VECTOR()
H A DTargetLowering.cpp5053 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactSDIV()
5171 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildSDIV()
5328 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildUDIV()
5851 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareSREMEqFold()
H A DDAGCombiner.cpp968 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
18551 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
19548 if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand) in visitBUILD_VECTOR()
19551 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); in visitBUILD_VECTOR()
H A DLegalizeDAG.cpp3738 case ISD::SPLAT_VECTOR: in ExpandNode()
H A DSelectionDAGBuilder.cpp3560 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1139 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1178 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1221 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1258 setOperationAction(ISD::SPLAT_VECTOR, MVT::nxv8bf16, Custom); in AArch64TargetLowering()
1503 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in addTypeForFixedLengthSVE()
4161 if (Splat.getOpcode() != ISD::SPLAT_VECTOR) in getGatherScatterIndexIsExtended()
4562 case ISD::SPLAT_VECTOR: in LowerOperation()
7188 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, TruncCC); in LowerSELECT()
7199 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal); in LowerSELECT()
9253 SDValue SplatOne = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, One); in LowerDUPQLane()
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H A DAArch64ISelDAGToDAG.cpp149 case ISD::SPLAT_VECTOR: { in SelectDupZeroOrUndef()
169 case ISD::SPLAT_VECTOR: { in SelectDupZero()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp813 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand); in initActions()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td666 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4500 if (N->getOpcode() == ISD::SPLAT_VECTOR) in isZeroVector()