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Searched refs:SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7856 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L macro
H A Dgfx_7_2_sh_mask.h8321 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 macro
H A Dgfx_8_1_sh_mask.h9973 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 macro
H A Dgfx_8_0_sh_mask.h9575 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15573 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
H A Dgc_9_2_1_sh_mask.h16757 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
H A Dgc_9_1_sh_mask.h16882 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
H A Dgc_10_1_0_sh_mask.h22951 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro