Home
last modified time | relevance | path

Searched refs:SIEncodingFamily (Results 1 – 14 of 14) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td30 SIMCInstr <NAME, SIEncodingFamily.NONE> {
56 : EXP_Real<_done, pseudo, SIEncodingFamily.SI>, EXPe {
70 : EXP_Real<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
84 : EXP_Real<_done, pseudo, SIEncodingFamily.GFX10>, EXPe {
H A DVOP2Instructions.td915 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
945 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
951 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
959 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
964 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
992 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1001 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1041 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1049 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1140 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
[all …]
H A DVOP3Instructions.td809 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
814 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>,
820 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
829 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
834 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
839 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
845 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
941 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
946 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
969 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
[all …]
H A DVOP1Instructions.td511 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10> {
537 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,
542 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
547 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
611 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
616 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
642 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
647 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
734 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
742 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
[all …]
H A DVOPInstructions.td48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
488 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> {
522 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
578 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
587 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>;
614 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> {
H A DVOP3PInstructions.td503 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
511 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
524 def _gfx90a_acd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
527 …def _gfx90a_vcd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64"), SIEncodingFamily.GFX90…
534 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
651 def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
H A DSIInstrInfo.td20 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
21 def SIEncodingFamily {
2333 SIMCInstr<opName, SIEncodingFamily.NONE> {
2350 SIMCInstr<opName, SIEncodingFamily.VI> {
2361 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm, SIEncodingFamily.SI>;
2367 def _gfx10 : VINTRP_Real_si<op, NAME, outs, ins, asm, SIEncodingFamily.GFX10>;
2441 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
2442 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
2443 [!cast<string>(SIEncodingFamily.VI)],
2444 [!cast<string>(SIEncodingFamily.SDWA)],
[all …]
H A DVOPCInstructions.td79 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
882 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
885 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
905 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>,
912 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>,
999 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
1002 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1228 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1232 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
H A DBUFInstructions.td66 SIMCInstr<opName, SIEncodingFamily.NONE> {
295 SIMCInstr<opName, SIEncodingFamily.NONE> {
1896 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
1902 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
2191 Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.GFX10> {
2224 Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.SI> {
2285 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.VI, has_sccb> {
2294 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.GFX90A, has_sccb> {
2357 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
2521 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.VI> {
[all …]
H A DSMInstructions.td27 SIMCInstr<opName, SIEncodingFamily.NONE> {
450 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
503 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
731 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
887 SM_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10>, Enc64 {
H A DDSInstructions.td11 SIMCInstr <opName, SIEncodingFamily.NONE> {
993 SIEncodingFamily.GFX10>;
1020 SIEncodingFamily.SI>;
1043 SIEncodingFamily.SI>;
1189 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
H A DSIInstrInfo.cpp7474 enum SIEncodingFamily { enum
7486 static SIEncodingFamily subtargetEncodingFamily(const GCNSubtarget &ST) { in subtargetEncodingFamily()
7492 return SIEncodingFamily::SI; in subtargetEncodingFamily()
7495 return SIEncodingFamily::VI; in subtargetEncodingFamily()
7497 return SIEncodingFamily::GFX10; in subtargetEncodingFamily()
7523 SIEncodingFamily Gen = subtargetEncodingFamily(ST); in pseudoToMCOpcode()
7527 Gen = SIEncodingFamily::GFX9; in pseudoToMCOpcode()
7533 Gen = SIEncodingFamily::GFX80; in pseudoToMCOpcode()
7538 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
7541 Gen = SIEncodingFamily::SDWA9; in pseudoToMCOpcode()
[all …]
H A DSOPInstructions.td25 SIMCInstr<opName, SIEncodingFamily.NONE> {
681 SIMCInstr<opName, SIEncodingFamily.NONE> {
1424 class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> {
1429 class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {
1434 class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {
H A DFLATInstructions.td23 SIMCInstr<opName, SIEncodingFamily.NONE> {
1317 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
1385 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
1561 FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {