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Searched refs:SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h650 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dsdma0_4_0_sh_mask.h651 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L macro
H A Dsdma0_4_2_sh_mask.h653 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dsdma0_4_2_2_sh_mask.h659 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1065 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
H A Doss_2_4_sh_mask.h1155 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
H A Doss_3_0_1_sh_mask.h1175 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
H A Doss_3_0_sh_mask.h1681 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h365 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro