Searched refs:SCVTF (Results 1 – 7 of 7) sorted by relevance
/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/ |
H A D | sljitNativeARM_64.c | 110 #define SCVTF 0x9e620000 macro 1655 FAIL_IF(push_inst(compiler, (SCVTF ^ inv_bits) | VD(dst_r) | RN(src))); in sljit_emit_fop1_conv_f64_from_sw()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedCyclone.td | 575 // SCVTF,UCVTF V,V
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H A D | AArch64InstrInfo.td | 3800 defm SCVTF : IntegerToFP<0, "scvtf", any_sint_to_fp>; 4176 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>; 4677 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>; 6210 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">; 6331 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", 6502 // SCVTF GPR -> FPR is 9 cycles. 6503 // SCVTF FPR -> FPR is 4 cyclces. 6505 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR 6557 // SCVTF on floating point registers (both source and destination
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/netbsd-src/external/gpl3/binutils/dist/gas/ |
H A D | ChangeLog-2019 | 1555 SCVTF, UCVTF, LSR and ASR.
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/netbsd-src/external/gpl3/binutils.old/dist/gas/ |
H A D | ChangeLog-2019 | 1555 SCVTF, UCVTF, LSR and ASR.
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
H A D | aarch64-sve.md | 8721 ;; - SCVTF
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
H A D | aarch64-sve.md | 9105 ;; - SCVTF
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