Searched refs:SCN_REG (Results 1 – 4 of 4) sorted by relevance
42 #define CH_MR SCN_REG(0) /* rw mode register */43 #define CH_SR SCN_REG(1) /* ro status register */44 #define CH_CSR SCN_REG(1) /* wo clock select reg */45 #define CH_CR SCN_REG(2) /* wo command reg */46 #define CH_DAT SCN_REG(3) /* rw data reg */49 #define DU_IPCR SCN_REG(4) /* ro input port change reg */50 #define DU_ACR SCN_REG(4) /* wo aux control reg */51 #define DU_ISR SCN_REG(5) /* ro interrupt stat reg */52 #define DU_IMR SCN_REG(5) /* wo interrupt mask reg */53 #define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */[all …]
85 #define SCN_REG(n) (n << 4) /* 15 byte pad after each reg */ macro
44 #define CH_MR(x) SCN_REG(0 + 8*(x)) /* rw mode register */45 #define CH_SR(x) SCN_REG(1 + 8*(x)) /* ro status register */46 #define CH_CSR(x) SCN_REG(1 + 8*(x)) /* wo clock select reg */47 #define CH_CR(x) SCN_REG(2 + 8*(x)) /* wo command reg */48 #define CH_DAT(x) SCN_REG(3 + 8*(x)) /* rw data reg */51 #define DU_IPCR SCN_REG(4) /* ro input port change reg */52 #define DU_ACR SCN_REG(4) /* wo aux control reg */53 #define DU_ISR SCN_REG(5) /* ro interrupt stat reg */54 #define DU_IMR SCN_REG(5) /* wo interrupt mask reg */55 #define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */[all …]
82 #define SCN_REG(n) ((n) << 1) /* DUART bytes are word aligned */ macro83 #define QVA_FIRSTREG SCN_REG(0)84 #define QVA_WINSIZE (SCN_REG(16) - SCN_REG(0))