Searched refs:Rsrc (Results 1 – 4 of 4) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 5131 const DebugLoc &DL, MachineOperand &Rsrc) { in emitLoadSRsrcFromVGPRLoop() argument 5149 Register VRsrc = Rsrc.getReg(); in emitLoadSRsrcFromVGPRLoop() 5150 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); in emitLoadSRsrcFromVGPRLoop() 5152 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI); in emitLoadSRsrcFromVGPRLoop() 5213 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop() 5214 Rsrc.setIsKill(true); in emitLoadSRsrcFromVGPRLoop() 5239 MachineOperand &Rsrc, MachineDominatorTree *MDT, in loadSRsrcFromVGPR() argument 5310 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc); in loadSRsrcFromVGPR() 5320 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) { in extractRsrcPtr() argument 5327 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass, in extractRsrcPtr() [all …]
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| H A D | SIISelLowering.h | 70 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
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| H A D | AMDGPUISelDAGToDAG.cpp | 1520 SDValue Addr, SDValue &Rsrc, in SelectMUBUFScratchOffen() argument 1528 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffen() 1630 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | in SelectMUBUFOffset() local 1637 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
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| H A D | SIISelLowering.cpp | 6307 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, in lowerSBuffer() argument 6324 Rsrc, in lowerSBuffer() 6362 Rsrc, // rsrc in lowerSBuffer()
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