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Searched refs:ResourceCycles (Results 1 – 25 of 58) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
417 let ResourceCycles = [2];
482 let ResourceCycles = [3];
487 let ResourceCycles = [3,1];
494 let ResourceCycles = [4,3,1,1];
499 let ResourceCycles = [4,3,1,1,1];
506 let ResourceCycles = [3];
511 let ResourceCycles = [3,1];
518 let ResourceCycles = [4,3,1];
[all …]
H A DX86SchedHaswell.td103 let ResourceCycles = Res;
111 let ResourceCycles = !listconcat([1], Res);
469 let ResourceCycles = [2];
492 let ResourceCycles = [3];
497 let ResourceCycles = [3,1];
504 let ResourceCycles = [4,3,1,1];
509 let ResourceCycles = [4,3,1,1,1];
516 let ResourceCycles = [3];
521 let ResourceCycles = [3,1];
528 let ResourceCycles = [4,3,1];
[all …]
H A DX86SchedBroadwell.td98 let ResourceCycles = Res;
106 let ResourceCycles = !listconcat([1], Res);
427 let ResourceCycles = [2];
491 let ResourceCycles = [3];
496 let ResourceCycles = [3,1];
503 let ResourceCycles = [4,3,1,1];
508 let ResourceCycles = [4,3,1,1,1];
515 let ResourceCycles = [3];
520 let ResourceCycles = [3,1];
527 let ResourceCycles = [4,3,1];
[all …]
H A DX86SchedSkylakeServer.td97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
418 let ResourceCycles = [2];
483 let ResourceCycles = [3];
488 let ResourceCycles = [3,1];
495 let ResourceCycles = [4,3,1,1];
500 let ResourceCycles = [4,3,1,1,1];
507 let ResourceCycles = [3];
512 let ResourceCycles = [3,1];
519 let ResourceCycles = [4,3,1];
[all …]
H A DX86ScheduleAtom.td63 let ResourceCycles = RRRes;
69 let ResourceCycles = RMRes;
118 let ResourceCycles = [2];
122 let ResourceCycles = [2];
456 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
457 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
459 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
489 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
490 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
499 let ResourceCycles = [1];
[all …]
H A DX86SchedSandyBridge.td93 let ResourceCycles = Res;
101 let ResourceCycles = !listconcat([1], Res);
473 let ResourceCycles = [3];
478 let ResourceCycles = [3,1];
484 let ResourceCycles = [8];
488 let ResourceCycles = [7, 1];
495 let ResourceCycles = [3];
500 let ResourceCycles = [3,1];
506 let ResourceCycles = [8];
510 let ResourceCycles = [7, 1];
[all …]
H A DX86ScheduleBdVer2.td195 let ResourceCycles = Res;
268 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
271 def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; }
276 def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
310 let ResourceCycles = [375];
318 def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
328 let ResourceCycles = [3, 2, 1];
335 let ResourceCycles = [88];
342 let ResourceCycles = [2];
354 let ResourceCycles = [3, 3];
[all …]
H A DX86ScheduleZnver3.td404 let ResourceCycles = Res;
499 let ResourceCycles = [3, 1];
513 let ResourceCycles = [1, 1, 4];
520 let ResourceCycles = [4, 1, 1];
530 let ResourceCycles = [4];
541 let ResourceCycles = [4];
548 let ResourceCycles = [2];
555 let ResourceCycles = [1];
565 let ResourceCycles = [1, 1, 7, 1];
576 let ResourceCycles = [1];
[all …]
H A DX86ScheduleBtVer2.td128 let ResourceCycles = Res;
136 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
148 let ResourceCycles = Res;
156 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
168 let ResourceCycles = Res;
176 let ResourceCycles = !listconcat([2], Res);
312 let ResourceCycles = [3];
318 let ResourceCycles = [3,16,16];
324 let ResourceCycles = [3,17,17];
330 let ResourceCycles = [3,1,1];
[all …]
H A DX86ScheduleZnver1.td139 let ResourceCycles = Res;
147 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
160 let ResourceCycles = Res;
168 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
458 let ResourceCycles = [1, 2];
463 let ResourceCycles = [1, 2, 3];
474 let ResourceCycles = [2];
662 let ResourceCycles = [1, 2];
669 let ResourceCycles = [1, 2, 2];
963 let ResourceCycles = [1,3];
[all …]
H A DX86ScheduleZnver2.td138 let ResourceCycles = Res;
146 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
159 let ResourceCycles = Res;
167 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
440 let ResourceCycles = [1, 2];
445 let ResourceCycles = [1, 2, 3];
456 let ResourceCycles = [2];
660 let ResourceCycles = [1, 2];
667 let ResourceCycles = [1, 2, 2];
972 let ResourceCycles = [1,3];
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DSupport.cpp23 ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) { in operator +=()
94 unsigned ResourceCycles = ProcResourceUsage[I]; in computeBlockRThroughput() local
95 if (!ResourceCycles) in computeBlockRThroughput()
99 double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits; in computeBlockRThroughput()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td231 let ResourceCycles = [8];
236 let ResourceCycles = [8];
241 let ResourceCycles = [8];
265 let ResourceCycles = [5];
270 let ResourceCycles = [8];
275 let ResourceCycles = [8];
280 let ResourceCycles = [5];
285 let ResourceCycles = [10];
290 let ResourceCycles = [10];
295 let ResourceCycles = [8];
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DSupport.h50 class ResourceCycles {
54 ResourceCycles() : Numerator(0), Denominator(1) {} in ResourceCycles() function
55 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
69 ResourceCycles &operator+=(const ResourceCycles &RHS);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td31 let ResourceCycles = [17]; }
33 let ResourceCycles = [18]; }
35 let ResourceCycles = [19]; }
37 let ResourceCycles = [20]; }
40 let ResourceCycles = [1]; }
42 let ResourceCycles = [1]; }
48 let ResourceCycles = [1]; }
50 let ResourceCycles = [32]; }
52 let ResourceCycles = [32]; }
54 let ResourceCycles = [35]; }
[all …]
H A DARMScheduleR52.td75 let Latency = 8; let ResourceCycles = [8]; // non-pipelined
110 let ResourceCycles = [7]; // is not pipelined
115 let ResourceCycles = [17];
148 let Latency = 8; let ResourceCycles = [8]; // not pipelined
555 let ResourceCycles = [Num];
642 let ResourceCycles = [1];
647 let ResourceCycles = [2];
652 let ResourceCycles = [3];
657 let ResourceCycles = [4];
662 let ResourceCycles = [5];
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td76 let Latency = 8; let ResourceCycles = [8];
79 let Latency = 8; let ResourceCycles = [8];
91 let ResourceCycles = [3]; }
94 let ResourceCycles = [2]; }
96 let ResourceCycles = [3]; }
98 let ResourceCycles = [4]; }
100 let ResourceCycles = [5]; }
102 let ResourceCycles = [6]; }
104 let ResourceCycles = [7]; }
106 let ResourceCycles = [8]; }
[all …]
H A DAArch64SchedThunderX.td60 let ResourceCycles = [1];
65 let ResourceCycles = [1];
71 let ResourceCycles = [6];
76 let ResourceCycles = [8];
87 let ResourceCycles = [3];
92 let ResourceCycles = [1];
97 let ResourceCycles = [7];
102 let ResourceCycles = [8];
107 let ResourceCycles = [9];
112 let ResourceCycles = [9];
[all …]
H A DAArch64SchedExynosM3.td116 let ResourceCycles = [2]; }
208 let ResourceCycles = [1, 12]; }
211 let ResourceCycles = [1, 21]; }
214 let ResourceCycles = [2]; }
239 let ResourceCycles = [12]; }
301 let ResourceCycles = [8, 8]; }
305 let ResourceCycles = [13, 13]; }
309 let ResourceCycles = [19, 19]; }
313 let ResourceCycles = [26, 26]; }
324 let ResourceCycles = [8]; }
[all …]
H A DAArch64SchedExynosM4.td143 let ResourceCycles = [2]; }
177 let ResourceCycles = [2]; }
180 let ResourceCycles = [12]; }
182 let ResourceCycles = [21]; }
266 let ResourceCycles = [6, 6]; }
269 let ResourceCycles = [6, 6]; }
272 let ResourceCycles = [9, 9]; }
275 let ResourceCycles = [7, 7]; }
278 let ResourceCycles = [6, 6]; }
281 let ResourceCycles = [9, 9]; }
[all …]
H A DAArch64SchedA53.td84 let ResourceCycles = [3]; }
87 let ResourceCycles = [2]; }
89 let ResourceCycles = [3]; }
91 let ResourceCycles = [4]; }
93 let ResourceCycles = [5]; }
107 let ResourceCycles = [2];}
110 let ResourceCycles = [2]; }
112 let ResourceCycles = [3]; }
134 let ResourceCycles = [29]; }
137 let ResourceCycles = [14]; }
[all …]
H A DAArch64SchedExynosM5.td143 let ResourceCycles = [2]; }
145 let ResourceCycles = [2]; }
195 let ResourceCycles = [2]; }
198 let ResourceCycles = [10]; }
200 let ResourceCycles = [16]; }
229 let ResourceCycles = [1, 1, 1, 1, 15]; }
236 let ResourceCycles = [1, 1, 1, 1, 15]; }
240 let ResourceCycles = [1, 13]; }
244 let ResourceCycles = [1, 13]; }
283 let ResourceCycles = [7, 7]; }
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td63 let ResourceCycles = [1, 15];
67 let ResourceCycles = [1, 15];
114 let ResourceCycles = [1, 26]; }
116 let ResourceCycles = [1, 26]; }
130 let ResourceCycles = [1, 55]; }
132 let ResourceCycles = [1, 55]; }
H A DRISCVSchedRocket.td70 let ResourceCycles = [34];
74 let ResourceCycles = [33];
158 let Latency = 20, ResourceCycles = [20] in {
165 let ResourceCycles = [20]; }
167 let ResourceCycles = [25]; }
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp54 SmallVector<std::pair<ResourceRef, ResourceCycles>, 4> Used; in issueInstruction()
254 MutableArrayRef<std::pair<ResourceRef, ResourceCycles>> Used) const { in notifyInstructionIssued()
257 for (const std::pair<ResourceRef, ResourceCycles> &Resource : Used) { in notifyInstructionIssued()
266 for (std::pair<ResourceRef, ResourceCycles> &Use : Used) in notifyInstructionIssued()

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