| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 39 using RegisterSet = SmallSet<unsigned, 4>; typedef
68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS()
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
113 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) { in ClearKillFlags()
138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 92 struct RegisterSet : private BitVector { struct
93 RegisterSet() = default;
94 explicit RegisterSet(unsigned s, bool t = false) : BitVector(s, t) {} in RegisterSet() argument
95 RegisterSet(const RegisterSet &RS) : BitVector(RS) {} in RegisterSet() function
96 RegisterSet &operator=(const RegisterSet &RS) { in operator =() argument
117 RegisterSet &insert(unsigned R) { in insert() argument
120 return static_cast<RegisterSet&>(BitVector::set(Idx)); in insert()
122 RegisterSet &remove(unsigned R) { in remove() argument
126 return static_cast<RegisterSet&>(BitVector::reset(Idx)); in remove()
129 RegisterSet &insert(const RegisterSet &Rs) { in insert() argument
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| H A D | HexagonBitSimplify.cpp | 75 struct RegisterSet : private BitVector { struct
76 RegisterSet() = default;
77 explicit RegisterSet(unsigned s, bool t = false) : BitVector(s, t) {} in RegisterSet() function
78 RegisterSet(const RegisterSet &RS) = default;
97 RegisterSet &insert(unsigned R) { in insert() argument
100 return static_cast<RegisterSet&>(BitVector::set(Idx)); in insert()
102 RegisterSet &remove(unsigned R) { in remove() argument
106 return static_cast<RegisterSet&>(BitVector::reset(Idx)); in remove()
109 RegisterSet &insert(const RegisterSet &Rs) { in insert() argument
110 return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); in insert()
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| H A D | HexagonBlockRanges.cpp | 232 HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns( in getLiveIns()
235 RegisterSet LiveIns; in getLiveIns()
236 RegisterSet Tmp; in getLiveIns()
261 HexagonBlockRanges::RegisterSet HexagonBlockRanges::expandToSubRegs( in expandToSubRegs()
264 RegisterSet SRs; in expandToSubRegs()
293 RegisterSet LiveOnEntry; in computeInitialLiveRanges()
313 RegisterSet Defs, Clobbers; in computeInitialLiveRanges()
397 RegisterSet LiveOnExit; in computeInitialLiveRanges()
406 RegisterSet Left; in computeInitialLiveRanges()
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| H A D | HexagonBlockRanges.h | 43 using RegisterSet = std::set<RegisterRef>; member
149 static RegisterSet expandToSubRegs(RegisterRef R,
164 RegisterSet getLiveIns(const MachineBasicBlock &B,
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | LivePhysRegs.h | 50 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>; variable
51 RegisterSet LiveRegs;
149 using const_iterator = RegisterSet::const_iterator;
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| H A D | RDFGraph.h | 412 using RegisterSet = std::set<RegisterRef>; variable
816 RegisterSet getLandingPadLiveIns() const;
841 using BlockRefsMap = std::map<NodeId, RegisterSet>;
845 void buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
955 raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterSet> &P);
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| H A D | TargetRegisterInfo.h | 1076 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1080 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 79 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, in markSuperRegs() argument
82 RegisterSet.set(*AI); in markSuperRegs()
85 bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, in checkAllSuperRegsMarked() argument
89 for (unsigned Reg : RegisterSet.set_bits()) { in checkAllSuperRegsMarked()
93 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { in checkAllSuperRegsMarked()
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| H A D | RDFGraph.cpp | 307 raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterSet> &P) { in operator <<()
748 RegisterSet DataFlowGraph::getLandingPadLiveIns() const { in getLandingPadLiveIns()
749 RegisterSet LR; in getLandingPadLiveIns()
889 RegisterSet AllRefs; in build()
921 RegisterSet EHRegs = getLandingPadLiveIns(); in build()
1396 RegisterSet Defs; in recordDefsForDF()
1420 void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs, in buildPhis()
1432 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { in buildPhis()
1439 RegisterSet MaxDF; in buildPhis()
1611 RegisterSet Defs; in linkStmtRefs()
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| H A D | LivePhysRegs.cpp | 33 RegisterSet::iterator LRI = LiveRegs.begin(); in removeRegsInMask()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | AsmMatcherEmitter.cpp | 141 typedef std::set<Record*, LessRecordByID> RegisterSet; typedef
203 RegisterSet Registers;
242 RegisterSet Tmp; in isRelatedTo()
243 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin()); in isRelatedTo()
1199 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const { in operator ()()
1215 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet; in buildRegisterClasses()
1223 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1227 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1)); in buildRegisterClasses()
1233 std::map<Record*, RegisterSet> RegisterMap; in buildRegisterClasses()
1236 RegisterSet ContainingSet; in buildRegisterClasses()
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