| /netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| H A D | xray_mips64.cc | 35 enum RegNum : uint32_t { enum
105 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_RA, 0x8); in patchSled()
107 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_T9, 0x0); in patchSled()
109 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HighestTracingHookAddr); in patchSled()
111 encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, in patchSled()
114 PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
116 PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, HiTracingHookAddr); in patchSled()
118 PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
120 PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr); in patchSled()
122 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID); in patchSled()
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| H A D | xray_mips.cc | 34 enum RegNum : uint32_t { enum
105 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4); in patchSled()
107 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0); in patchSled()
109 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr); in patchSled()
111 PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr); in patchSled()
113 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID); in patchSled()
115 PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0); in patchSled()
117 PatchOpcodes::PO_ORI, RegNum::RN_T0, RegNum::RN_T0, LoFunctionID); in patchSled()
119 PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_T9, 0x0); in patchSled()
121 PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_RA, 0x4); in patchSled()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
74 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
76 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum, in getLLVMRegNum() argument
88 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
90 if (I != M + Size && I->FromReg == RegNum) in getLLVMRegNum()
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { in getDwarfRegNumFromDwarfEHRegNum()
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) in getDwarfRegNumFromDwarfEHRegNum()
106 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.cpp | 33 unsigned RegNum) { in printRegister() argument
35 if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(RegNum, IsEH)) { in printRegister()
42 OS << "reg" << RegNum; in printRegister()
63 UnwindLocation UnwindLocation::createIsRegisterPlusOffset(uint32_t RegNum, in createIsRegisterPlusOffset() argument
65 return {RegPlusOffset, RegNum, Offset, false}; in createIsRegisterPlusOffset()
67 UnwindLocation UnwindLocation::createAtRegisterPlusOffset(uint32_t RegNum, in createAtRegisterPlusOffset() argument
69 return {RegPlusOffset, RegNum, Offset, true}; in createAtRegisterPlusOffset()
103 printRegister(OS, MRI, IsEH, RegNum); in dump()
138 return RegNum == RHS.RegNum && Offset == RHS.Offset && in operator ==()
356 uint64_t RegNum = Data.getULEB128(C); in parse() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
68 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
72 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 206 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
208 return std::make_unique<AVROperand>(RegNum, S, E); in CreateReg()
217 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { in CreateMemri() argument
218 return std::make_unique<AVROperand>(RegNum, Val, S, E); in CreateMemri()
338 int RegNum = matchFn(Name); in parseRegisterName() local
344 if (RegNum == AVR::NoRegister) { in parseRegisterName()
345 RegNum = matchFn(Name.lower()); in parseRegisterName()
347 if (RegNum == AVR::NoRegister) { in parseRegisterName()
348 RegNum = matchFn(Name.upper()); in parseRegisterName()
351 return RegNum; in parseRegisterName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.h | 65 uint32_t RegNum; /// The register number for Kind == RegPlusOffset. variable
75 : Kind(K), RegNum(InvalidRegisterNumber), Offset(0), Dereference(false) {} in UnwindLocation()
78 : Kind(K), RegNum(Reg), Offset(Off), Dereference(Deref) {} in UnwindLocation()
81 : Kind(DWARFExpr), RegNum(InvalidRegisterNumber), Offset(0), Expr(E), in UnwindLocation()
120 uint32_t getRegister() const { return RegNum; } in getRegister()
126 void setRegister(uint32_t NewRegNum) { RegNum = NewRegNum; } in setRegister()
174 Optional<UnwindLocation> getRegisterLocation(uint32_t RegNum) const { in getRegisterLocation() argument
175 auto Pos = Locations.find(RegNum); in getRegisterLocation()
186 void setRegisterLocation(uint32_t RegNum, const UnwindLocation &Location) { in setRegisterLocation() argument
187 Locations.erase(RegNum); in setRegisterLocation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRInstPrinter.cpp | 89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, in getPrettyRegisterName() argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; in getPrettyRegisterName()
98 return getRegisterName(RegNum); in getPrettyRegisterName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 207 unsigned RegNum; member
254 return Reg.RegNum; in getReg()
433 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
435 Op->Reg.RegNum = RegNum; in CreateReg()
1779 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1780 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1782 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
1787 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum); in processInstruction()
1796 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1797 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 198 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
200 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E); in CreateReg()
208 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, in CreateMem() argument
211 return std::make_unique<MSP430Operand>(RegNum, Val, S, E); in CreateMem()
214 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, in CreateIndReg() argument
216 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E); in CreateIndReg()
219 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, in CreatePostIndReg() argument
221 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E); in CreatePostIndReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 69 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
123 unsigned RegNum; member
158 return Reg.RegNum; in getReg()
594 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, in createReg()
597 Op->Reg.RegNum = RegNum; in createReg()
698 unsigned RegNum; in parseRegister() local
705 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); in parseRegister()
706 if (RegNum == 0) { in parseRegister()
712 return LanaiOperand::createReg(RegNum, Start, End); in parseRegister()
719 bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, in ParseRegister() argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 348 unsigned RegNum; member
374 unsigned RegNum; member
580 return Reg.RegNum; in getReg()
590 return VectorList.RegNum; in getVectorListStart()
1087 Reg.RegNum) || in isNeonVectorRegLo()
1089 Reg.RegNum)); in isNeonVectorRegLo()
1164 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
1169 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum); in isGPR64as32()
1175 Reg.RegNum); in isGPR64x8()
1181 Reg.RegNum); in isWSeqPair()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 173 unsigned RegNum; member
346 return Reg.RegNum; in getReg()
596 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
599 Op->Reg.RegNum = RegNum; in CreateReg()
647 Op.Reg.RegNum = I32Regs[regIdx]; in MorphToI32Reg()
656 Op.Reg.RegNum = F32Regs[regIdx]; in MorphToF32Reg()
665 Op.Reg.RegNum = F128Regs[regIdx / 2]; in MorphToF128Reg()
674 Op.Reg.RegNum = VM512Regs[regIdx / 2]; in MorphToVM512Reg()
686 Op.Reg.RegNum = MISCRegs[regIdx]; in MorphToMISCReg()
808 int RegNum = matchFn(Name); in parseRegisterName() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 513 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
517 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
521 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
525 int getSEHRegNum(MCRegister RegNum) const;
529 int getCodeViewRegNum(MCRegister RegNum) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | InstructionSelectorImpl.h | 903 int64_t RegNum = MatchTable[CurrentIdx++]; in executeMatchTable() local
905 OutMIs[InsnID].addDef(RegNum, RegState::Implicit); in executeMatchTable()
908 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
914 int64_t RegNum = MatchTable[CurrentIdx++]; in executeMatchTable() local
916 OutMIs[InsnID].addUse(RegNum, RegState::Implicit); in executeMatchTable()
919 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
925 int64_t RegNum = MatchTable[CurrentIdx++]; in executeMatchTable() local
928 OutMIs[InsnID].addReg(RegNum, RegFlags); in executeMatchTable()
932 << InsnID << "], " << RegNum << ", " << RegFlags << ")\n"); in executeMatchTable()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 154 unsigned RegNum = MCO.getReg(); in encodeReg() local
159 uint32_t Val = RI->getEncodingValue(RegNum); in encodeReg()
166 Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset; in encodeReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 179 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum() local
180 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
181 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
183 assert(RegNum >= 0 && "Invalid Dwarf register number."); in getDwarfRegNum()
184 return (unsigned)RegNum; in getDwarfRegNum()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 280 auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum, in DecodeMoveHRegInstruction()
282 if (30 == RegNum) { in DecodeMoveHRegInstruction()
287 return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder); in DecodeMoveHRegInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 238 unsigned RegNum; member
324 return Reg.RegNum; in getReg()
438 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() argument
441 Op->Reg.RegNum = RegNum; in CreateReg()
471 Op.Reg.RegNum = IntPairRegs[regIdx / 2]; in MorphToIntPairReg()
482 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
505 Op.Reg.RegNum = Reg; in MorphToQuadReg()
518 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2]; in MorphToCoprocPairReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.h | 47 int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 90 unsigned RegNum; member
150 return Reg.RegNum; in getReg()
209 Op->Reg.RegNum = RegNo; in createReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 826 unsigned RegNum; member
831 unsigned RegNum; member
860 unsigned RegNum; member
966 return Reg.RegNum; in getReg()
1446 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
2029 VectorList.RegNum); in isVecListTwoMQ()
2035 .contains(VectorList.RegNum)); in isVecListDPair()
2052 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
2068 VectorList.RegNum); in isVecListFourMQ()
2087 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/Basic/ |
| H A D | TargetInfo.cpp | 519 if (AN == Name && ARN.RegNum < Names.size()) in isValidGCCRegisterName()
560 if (AN == Name && ARN.RegNum < Names.size()) in getNormalizedGCCRegisterName()
561 return ReturnCanonical ? Names[ARN.RegNum] : Name; in getNormalizedGCCRegisterName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 91 unsigned RegNum; member
198 return Reg.RegNum; in getReg()
236 Op->Reg.RegNum = RegNo; in createReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1234 unsigned &RegNum, unsigned &RegWidth,
1237 unsigned &RegNum, unsigned &RegWidth,
1239 unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1242 unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1245 unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1249 unsigned RegNum,
2434 unsigned RegNum, in getRegularReg() argument
2447 if (RegNum % AlignSize != 0) { in getRegularReg()
2452 unsigned RegIdx = RegNum / AlignSize; in getRegularReg()
2513 unsigned &RegNum, unsigned &RegWidth, in ParseSpecialReg() argument
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