| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 30 const RegisterClassInfo &RegClassInfo, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | BreakFalseDeps.cpp | 38 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
286 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
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| H A D | RegAllocBase.cpp | 65 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| H A D | RegAllocBase.h | 69 RegisterClassInfo RegClassInfo; variable
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| H A D | PostRASchedulerList.cpp | 80 RegisterClassInfo RegClassInfo; member in __anon3e4a0d930111::PostRAScheduler
289 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
312 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| H A D | RegAllocFast.cpp | 79 RegisterClassInfo RegClassInfo; member in __anondcfd0db60111::RegAllocFast
777 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
830 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
961 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1195 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()
1196 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
1523 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocGreedy.cpp | 855 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in canReassign()
967 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterference()
968 RegClassInfo.getNumAllocatableRegs( in canEvictInterference()
1139 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
1171 uint8_t MinCost = RegClassInfo.getMinCost(RC); in tryEvict()
1181 OrderLimit = RegClassInfo.getLastCostChange(RC); in tryEvict()
1198 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1710 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
2031 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
2097 if (!RegClassInfo.isProperSubClass(CurRC)) in tryInstructionSplit()
[all …]
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| H A D | MachineCombiner.cpp | 76 RegisterClassInfo RegClassInfo; member in __anonc479f2030111::MachineCombiner
561 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo); in combineInstructions()
722 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | AllocationOrder.h | 85 const RegisterClassInfo &RegClassInfo,
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| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; variable
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| H A D | CriticalAntiDepBreaker.cpp | 45 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | MachineScheduler.cpp | 155 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
159 delete RegClassInfo; in ~MachineSchedContext()
404 RegClassInfo->runOnMachineFunction(*MF); in runOnMachineFunction()
1018 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1020 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1072 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1102 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1285 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
2943 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
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| H A D | RegAllocBasic.cpp | 268 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| H A D | MachineSink.cpp | 124 RegisterClassInfo RegClassInfo; member in __anon5856ea890111::MachineSinking
430 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
714 RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(), in getBBRegisterPressure()
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| H A D | AggressiveAntiDepBreaker.cpp | 125 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| H A D | TargetRegisterInfo.cpp | 57 const RegClassInfo *const RCIs, in TargetRegisterInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 38 RegisterClassInfo RegClassInfo; member in __anon62c696f20111::SIPreAllocateWWMRegs
103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
211 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | GCNSchedStrategy.cpp | 39 SGPRExcessLimit = Context->RegClassInfo in initialize()
41 VGPRExcessLimit = Context->RegClassInfo in initialize()
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| H A D | SIMachineScheduler.h | 446 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 235 struct RegClassInfo { struct
247 const RegClassInfo *const RCInfos; argument
257 const RegClassInfo *const RCIs,
719 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| H A D | MachineScheduler.h | 128 RegisterClassInfo *RegClassInfo; member
387 RegisterClassInfo *RegClassInfo;
431 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| H A D | MachinePipeliner.h | 68 RegisterClassInfo RegClassInfo; variable
116 const RegisterClassInfo &RegClassInfo; variable
197 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) { in SwingSchedulerDAG()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.h | 99 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 367 RegisterClassInfo *RegClassInfo) const override;
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